Claude review: arm64: dts: qcom: sc8280xp: Add dsi nodes on SC8280XP

Claude review: arm64: dts: qcom: sc8280xp: Add dsi nodes on SC8280XP

[Claude Code Review Bot]

Patch Review

**Status: Has bugs that need fixing.**

This is the main DTS patch adding 4 DSI controllers and 4 DSI PHYs across both MDSS instances. Overall structure looks correct, but there are two issues:

#### Bug 1: Missing comma in PHY compatible strings (CRITICAL)

All four PHY nodes are missing a comma between the two compatible strings. This will cause a DTS compilation error.

For `mdss0_dsi0_phy`:
```dts
+			compatible = "qcom,sc8280xp-dsi-phy-5nm"
+				     "qcom,sa8775p-dsi-phy-5nm";
```

Should be:
```dts
+			compatible = "qcom,sc8280xp-dsi-phy-5nm",
+				     "qcom,sa8775p-dsi-phy-5nm";
```

This same missing comma is present in all four PHY nodes: `mdss0_dsi0_phy`, `mdss0_dsi1_phy`, `mdss1_dsi0_phy`, and `mdss1_dsi1_phy`.

#### Bug 2: Copy-paste error in mdss1_dsi0 assigned-clock-parents

For `mdss1_dsi0`, the byte clock parent references the wrong PHY:

```dts
+			assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>,
+						 <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>;
```

The byte clock parent should reference `&mdss1_dsi0_phy` (not `&mdss1_dsi1_phy`), matching the pattern in `mdss0_dsi0` where both clock parents come from the same PHY:

```dts
			assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>,
						 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>;
```

This is likely a copy-paste error from the mdss1_dsi1 block.

#### Minor observations (not blocking)

- The `dsi_opp_table` is defined inside `mdss0_dsi0` and shared by reference from all four DSI controllers. This is correct per v2 review feedback from Konrad.
- The `#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>` header provides the `DSI_BYTE_PLL_CLK` and `DSI_PIXEL_PLL_CLK` defines. Despite the "28nm" in the filename, these constants are generic and used across PHY generations.
- The `refgen-supply` is correctly present on all four DSI controllers, addressing v3 feedback from Dmitry.
- The whitespace-only changes (adding blank lines between `reg` and endpoint labels) in existing port nodes are valid style cleanups.
- The commit message honestly notes that DSI won't fully work yet due to pending dispcc fixes and DSC timing issues. This is good transparency.

---
Generated by Claude Code Patch Reviewer

Claude review: arm64: dts: qcom: sc8280xp: Add dsi nodes on SC8280XP

[Claude Code Review Bot]

Patch Review

**Status: Needs fixes - has critical errors**

This is the main patch adding DSI controller and PHY nodes for both MDSS instances (mdss0 and mdss1), each with two DSI controllers and two DSI PHYs (4 controllers + 4 PHYs total). It also wires up the dispcc clock sources properly.

#### Bug 1 (Critical): Missing comma in all PHY compatible strings

All four PHY nodes have a missing comma between the two compatible strings:

```dts
+			mdss0_dsi0_phy: phy@ae94400 {
+				compatible = "qcom,sc8280xp-dsi-phy-5nm"
+					     "qcom,sa8775p-dsi-phy-5nm";
```

This appears identically in `mdss0_dsi0_phy`, `mdss0_dsi1_phy`, `mdss1_dsi0_phy`, and `mdss1_dsi1_phy`. Without the comma, dtc will concatenate the two strings into a single nonsensical compatible string `"qcom,sc8280xp-dsi-phy-5nmqcom,sa8775p-dsi-phy-5nm"`, which won't match any driver.

It should be:
```dts
				compatible = "qcom,sc8280xp-dsi-phy-5nm",
					     "qcom,sa8775p-dsi-phy-5nm";
```

Note: the DSI controller nodes have the comma correctly:
```dts
+				compatible = "qcom,sc8280xp-dsi-ctrl",
+					     "qcom,sa8775p-dsi-ctrl",
+					     "qcom,mdss-dsi-ctrl";
```

So this is clearly an oversight in the PHY nodes only.

#### Bug 2 (Likely copy-paste error): mdss1_dsi0 assigned-clock-parents mismatch

The `mdss1_dsi0` node has inconsistent clock parent PHY references:

```dts
+			mdss1_dsi0: dsi@22094000 {
+				...
+				assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>,
+							 <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>;
```

The byte clock parent references `mdss1_dsi1_phy` (DSI **1** PHY) while the pixel clock parent references `mdss1_dsi0_phy` (DSI **0** PHY). Comparing with the other three controllers:

- `mdss0_dsi0`: both from `mdss0_dsi0_phy` -- consistent
- `mdss0_dsi1`: both from `mdss0_dsi1_phy` -- consistent
- `mdss1_dsi0`: byte from `mdss1_dsi1_phy`, pixel from `mdss1_dsi0_phy` -- **inconsistent**
- `mdss1_dsi1`: both from `mdss1_dsi1_phy` -- consistent

This looks like a copy-paste error. It should likely be:
```dts
				assigned-clock-parents = <&mdss1_dsi0_phy DSI_BYTE_PLL_CLK>,
							 <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>;
```

#### Observation: 28nm clock header for 5nm PHY

```diff
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
```

This is technically correct -- `DSI_BYTE_PLL_CLK` and `DSI_PIXEL_PLL_CLK` are generic clock index defines that live in the 28nm header and are reused across all PHY generations. Other recent SoC dtsi files (SA8775P, etc.) do the same. But it could confuse future readers given the PHY is 5nm.

#### Observation: Shared OPP table placement

The `dsi_opp_table` is defined inside the `mdss0_dsi0` node but referenced by all four DSI controllers via phandle. This works functionally but is slightly unusual -- typically shared tables are placed at a common parent level. This was apparently requested by Konrad in v1 review, so it's intentional.

#### Observation: Style-only blank line additions

The patch adds blank lines after `reg = <N>;` in several existing port nodes (port@0, port@4, port@5, port@6 in both MDSS instances). This improves style consistency with the new port nodes but mixes style cleanup with functional changes. Likely acceptable since it was probably requested in v1 review.

#### Overall patch 4 structure

The DSI controller nodes are well-structured with correct interrupt numbers (4 for DSI0, 5 for DSI1), correct register addresses, proper clock assignments, and correct endpoint wiring. The dispcc clock source replacements from `<0>` stubs to actual PHY clock references are correct and necessary.

---

**Summary of required fixes:**
1. Add missing comma in all 4 PHY compatible strings
2. Fix `mdss1_dsi0` assigned-clock-parents to consistently reference `mdss1_dsi0_phy`

---
Generated by Claude Code Patch Reviewer

[PATCH v4 0/4] Add DSI display support for SC8280XP

[Pengyu Luo]

Add DSI display support for SC8280XP.
---
Changes in v4:
- add missing comma in DT
- collect tags
- Link to v3: https://lore.kernel.org/linux-arm-msm/20260228141715.35307-1-mitltlatltl@gmail.com

Changes in v3:
- add the missing refgen supply to DSI (Dmitry)
- Link to v2: https://lore.kernel.org/linux-arm-msm/20260228101907.18043-1-mitltlatltl@gmail.com

Changes in v2:
- fallback to SA8775P compatible (Krzysztof, Konrad, Dmitry)
- fix DT styles[a newline between property and subnode, property order] (Konrad)
- use one dsi_opp_table and all dsi controllers reference it (Konrad)
- resize dsi_pll region to 0x280 (Konrad)
- update commit message
- Link to v1: https://lore.kernel.org/linux-arm-msm/20260225054525.6803-1-mitltlatltl@gmail.com


Pengyu Luo (4):
  dt-bindings: display: msm-dsi-phy-7nm: Add SC8280XP
  dt-bindings: display/msm: dsi-controller-main: Add SC8280XP
  dt-bindings: display: msm: Document DSI controller and DSI PHY on
    SC8280XP
  arm64: dts: qcom: sc8280xp: Add dsi nodes on SC8280XP

 .../display/msm/dsi-controller-main.yaml      |   1 +
 .../bindings/display/msm/dsi-phy-7nm.yaml     |   1 +
 .../display/msm/qcom,sc8280xp-mdss.yaml       |  30 ++
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi        | 404 +++++++++++++++++-
 4 files changed, 428 insertions(+), 8 deletions(-)

-- 
2.53.0

[PATCH v4 1/4] dt-bindings: display: msm-dsi-phy-7nm: Add SC8280XP

[Pengyu Luo]

Since SC8280XP and SA8775P have the same values for the REVISION_ID
registers, then we fallback to SA8775P compatible.

Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
v4: There were no changes to the patch.
---
 Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
index 9a9a6c4abf..532f371829 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
@@ -32,6 +32,7 @@ properties:
       - items:
           - enum:
               - qcom,qcs8300-dsi-phy-5nm
+              - qcom,sc8280xp-dsi-phy-5nm
           - const: qcom,sa8775p-dsi-phy-5nm
 
   reg:
-- 
2.53.0

[PATCH v4 2/4] dt-bindings: display/msm: dsi-controller-main: Add SC8280XP

[Pengyu Luo]

Since SC8280XP and SA8775P have the same DSI version(2.5.1), then we
fallback to SA8775P compatible.

Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
v4: There were no changes to the patch.
---
 .../devicetree/bindings/display/msm/dsi-controller-main.yaml     | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index eb6d38dabb..617dd110db 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -49,6 +49,7 @@ properties:
       - items:
           - enum:
               - qcom,qcs8300-dsi-ctrl
+              - qcom,sc8280xp-dsi-ctrl
           - const: qcom,sa8775p-dsi-ctrl
           - const: qcom,mdss-dsi-ctrl
       - enum:
-- 
2.53.0

[PATCH v4 3/4] dt-bindings: display: msm: Document DSI controller and DSI PHY on SC8280XP

[Pengyu Luo]

Document DSI controller and DSI phy on SC8280XP platform.

Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
v4: There were no changes to the patch.
---
 .../display/msm/qcom,sc8280xp-mdss.yaml       | 30 +++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml
index af79406e16..a710cc84ec 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml
@@ -50,6 +50,22 @@ patternProperties:
           - qcom,sc8280xp-dp
           - qcom,sc8280xp-edp
 
+  "^dsi@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+    properties:
+      compatible:
+        contains:
+          const: qcom,sc8280xp-dsi-ctrl
+
+  "^phy@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+    properties:
+      compatible:
+        contains:
+          const: qcom,sc8280xp-dsi-phy-5nm
+
 unevaluatedProperties: false
 
 examples:
@@ -129,6 +145,20 @@ examples:
                     };
                 };
 
+                port@1 {
+                    reg = <1>;
+                    dpu_intf1_out: endpoint {
+                        remote-endpoint = <&mdss0_dsi0_in>;
+                    };
+                };
+
+                port@2 {
+                    reg = <2>;
+                    dpu_intf2_out: endpoint {
+                        remote-endpoint = <&mdss0_dsi1_in>;
+                    };
+                };
+
                 port@4 {
                     reg = <4>;
                     endpoint {
-- 
2.53.0

[PATCH v4 4/4] arm64: dts: qcom: sc8280xp: Add dsi nodes on SC8280XP

[Pengyu Luo]

The DT configuration follows other Samsung 5nm-based Qualcomm SOCs,
utilizing the same register layouts and clock structures.

However, DSI won't work properly for now until we submit dispcc fixes.
And some DSC enabled panels require DPU timing calculation fixes too.
(hdisplay / width timing round errors cause the fifo error)

Co-developed-by: Tianyu Gao <gty0622@gmail.com>
Signed-off-by: Tianyu Gao <gty0622@gmail.com>
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Tested-by: White Lewis <liu224806@gmail.com> # HUAWEI Gaokun3
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
v4: add missing comma
---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 404 ++++++++++++++++++++++++-
 1 file changed, 396 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 706eb1309d..73d38f1d69 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
@@ -4652,13 +4653,31 @@ ports {
 
 					port@0 {
 						reg = <0>;
+
 						mdss0_intf0_out: endpoint {
 							remote-endpoint = <&mdss0_dp0_in>;
 						};
 					};
 
+					port@1 {
+						reg = <1>;
+
+						mdss0_intf1_out: endpoint {
+							remote-endpoint = <&mdss0_dsi0_in>;
+						};
+					};
+
+					port@2 {
+						reg = <2>;
+
+						mdss0_intf2_out: endpoint {
+							remote-endpoint = <&mdss0_dsi1_in>;
+						};
+					};
+
 					port@4 {
 						reg = <4>;
+
 						mdss0_intf4_out: endpoint {
 							remote-endpoint = <&mdss0_dp1_in>;
 						};
@@ -4666,6 +4685,7 @@ mdss0_intf4_out: endpoint {
 
 					port@5 {
 						reg = <5>;
+
 						mdss0_intf5_out: endpoint {
 							remote-endpoint = <&mdss0_dp3_in>;
 						};
@@ -4673,6 +4693,7 @@ mdss0_intf5_out: endpoint {
 
 					port@6 {
 						reg = <6>;
+
 						mdss0_intf6_out: endpoint {
 							remote-endpoint = <&mdss0_dp2_in>;
 						};
@@ -4791,6 +4812,189 @@ opp-810000000 {
 				};
 			};
 
+			mdss0_dsi0: dsi@ae94000 {
+				compatible = "qcom,sc8280xp-dsi-ctrl",
+					     "qcom,sa8775p-dsi-ctrl",
+					     "qcom,mdss-dsi-ctrl";
+				reg = <0 0x0ae94000 0 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss0>;
+				interrupts = <4>;
+
+				clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK>,
+					 <&dispcc0 DISP_CC_MDSS_BYTE0_INTF_CLK>,
+					 <&dispcc0 DISP_CC_MDSS_PCLK0_CLK>,
+					 <&dispcc0 DISP_CC_MDSS_ESC0_CLK>,
+					 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+					 <&gcc GCC_DISP_HF_AXI_CLK>;
+				clock-names = "byte",
+					      "byte_intf",
+					      "pixel",
+					      "core",
+					      "iface",
+					      "bus";
+
+				assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK_SRC>,
+						  <&dispcc0 DISP_CC_MDSS_PCLK0_CLK_SRC>;
+				assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>,
+							 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>;
+
+				operating-points-v2 = <&dsi_opp_table>;
+				power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+				refgen-supply = <&refgen>;
+
+				phys = <&mdss0_dsi0_phy>;
+				phy-names = "dsi";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdss0_dsi0_in: endpoint {
+							remote-endpoint = <&mdss0_intf1_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						mdss0_dsi0_out: endpoint {
+						};
+					};
+				};
+
+				dsi_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-187500000 {
+						opp-hz = /bits/ 64 <187500000>;
+						required-opps = <&rpmhpd_opp_low_svs>;
+					};
+
+					opp-300000000 {
+						opp-hz = /bits/ 64 <300000000>;
+						required-opps = <&rpmhpd_opp_svs>;
+					};
+
+					opp-358000000 {
+						opp-hz = /bits/ 64 <358000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+				};
+			};
+
+			mdss0_dsi0_phy: phy@ae94400 {
+				compatible = "qcom,sc8280xp-dsi-phy-5nm",
+					     "qcom,sa8775p-dsi-phy-5nm";
+				reg = <0 0x0ae94400 0 0x200>,
+				      <0 0x0ae94600 0 0x280>,
+				      <0 0x0ae94900 0 0x280>;
+				reg-names = "dsi_phy",
+					    "dsi_phy_lane",
+					    "dsi_pll";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+					 <&rpmhcc RPMH_CXO_CLK>;
+				clock-names = "iface", "ref";
+
+				status = "disabled";
+			};
+
+			mdss0_dsi1: dsi@ae96000 {
+				compatible = "qcom,sc8280xp-dsi-ctrl",
+					     "qcom,sa8775p-dsi-ctrl",
+					     "qcom,mdss-dsi-ctrl";
+				reg = <0 0x0ae96000 0 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss0>;
+				interrupts = <5>;
+
+				clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK>,
+					 <&dispcc0 DISP_CC_MDSS_BYTE1_INTF_CLK>,
+					 <&dispcc0 DISP_CC_MDSS_PCLK1_CLK>,
+					 <&dispcc0 DISP_CC_MDSS_ESC1_CLK>,
+					 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+					 <&gcc GCC_DISP_HF_AXI_CLK>;
+				clock-names = "byte",
+					      "byte_intf",
+					      "pixel",
+					      "core",
+					      "iface",
+					      "bus";
+
+				assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK_SRC>,
+						  <&dispcc0 DISP_CC_MDSS_PCLK1_CLK_SRC>;
+				assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>,
+							 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>;
+
+				operating-points-v2 = <&dsi_opp_table>;
+				power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+				refgen-supply = <&refgen>;
+
+				phys = <&mdss0_dsi1_phy>;
+				phy-names = "dsi";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdss0_dsi1_in: endpoint {
+							remote-endpoint = <&mdss0_intf2_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						mdss0_dsi1_out: endpoint {
+						};
+					};
+				};
+			};
+
+			mdss0_dsi1_phy: phy@ae96400 {
+				compatible = "qcom,sc8280xp-dsi-phy-5nm",
+					     "qcom,sa8775p-dsi-phy-5nm";
+				reg = <0 0x0ae96400 0 0x200>,
+				      <0 0x0ae96600 0 0x280>,
+				      <0 0x0ae96900 0 0x280>;
+				reg-names = "dsi_phy",
+					    "dsi_phy_lane",
+					    "dsi_pll";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
+					 <&rpmhcc RPMH_CXO_CLK>;
+				clock-names = "iface", "ref";
+
+				status = "disabled";
+			};
+
 			mdss0_dp1: displayport-controller@ae98000 {
 				compatible = "qcom,sc8280xp-dp";
 				reg = <0 0xae98000 0 0x200>,
@@ -5080,10 +5284,10 @@ dispcc0: clock-controller@af00000 {
 				 <&mdss0_dp2_phy 1>,
 				 <&mdss0_dp3_phy 0>,
 				 <&mdss0_dp3_phy 1>,
-				 <0>,
-				 <0>,
-				 <0>,
-				 <0>;
+				 <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>,
+				 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>,
+				 <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>,
+				 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>;
 			power-domains = <&rpmhpd SC8280XP_MMCX>;
 
 			#clock-cells = <1>;
@@ -6011,13 +6215,31 @@ ports {
 
 					port@0 {
 						reg = <0>;
+
 						mdss1_intf0_out: endpoint {
 							remote-endpoint = <&mdss1_dp0_in>;
 						};
 					};
 
+					port@1 {
+						reg = <1>;
+
+						mdss1_intf1_out: endpoint {
+							remote-endpoint = <&mdss1_dsi0_in>;
+						};
+					};
+
+					port@2 {
+						reg = <2>;
+
+						mdss1_intf2_out: endpoint {
+							remote-endpoint = <&mdss1_dsi1_in>;
+						};
+					};
+
 					port@4 {
 						reg = <4>;
+
 						mdss1_intf4_out: endpoint {
 							remote-endpoint = <&mdss1_dp1_in>;
 						};
@@ -6025,6 +6247,7 @@ mdss1_intf4_out: endpoint {
 
 					port@5 {
 						reg = <5>;
+
 						mdss1_intf5_out: endpoint {
 							remote-endpoint = <&mdss1_dp3_in>;
 						};
@@ -6032,6 +6255,7 @@ mdss1_intf5_out: endpoint {
 
 					port@6 {
 						reg = <6>;
+
 						mdss1_intf6_out: endpoint {
 							remote-endpoint = <&mdss1_dp2_in>;
 						};
@@ -6147,6 +6371,170 @@ opp-810000000 {
 				};
 			};
 
+			mdss1_dsi0: dsi@22094000 {
+				compatible = "qcom,sc8280xp-dsi-ctrl",
+					     "qcom,sa8775p-dsi-ctrl",
+					     "qcom,mdss-dsi-ctrl";
+				reg = <0 0x22094000 0 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss1>;
+				interrupts = <4>;
+
+				clocks = <&dispcc1 DISP_CC_MDSS_BYTE0_CLK>,
+					 <&dispcc1 DISP_CC_MDSS_BYTE0_INTF_CLK>,
+					 <&dispcc1 DISP_CC_MDSS_PCLK0_CLK>,
+					 <&dispcc1 DISP_CC_MDSS_ESC0_CLK>,
+					 <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+					 <&gcc GCC_DISP_HF_AXI_CLK>;
+				clock-names = "byte",
+					      "byte_intf",
+					      "pixel",
+					      "core",
+					      "iface",
+					      "bus";
+
+				assigned-clocks = <&dispcc1 DISP_CC_MDSS_BYTE0_CLK_SRC>,
+						  <&dispcc1 DISP_CC_MDSS_PCLK0_CLK_SRC>;
+				assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>,
+							 <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>;
+
+				operating-points-v2 = <&dsi_opp_table>;
+				power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+				refgen-supply = <&refgen>;
+
+				phys = <&mdss1_dsi0_phy>;
+				phy-names = "dsi";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdss1_dsi0_in: endpoint {
+							remote-endpoint = <&mdss1_intf1_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						mdss1_dsi0_out: endpoint {
+						};
+					};
+				};
+			};
+
+			mdss1_dsi0_phy: phy@22094400 {
+				compatible = "qcom,sc8280xp-dsi-phy-5nm",
+					     "qcom,sa8775p-dsi-phy-5nm";
+				reg = <0 0x22094400 0 0x200>,
+				      <0 0x22094600 0 0x280>,
+				      <0 0x22094900 0 0x280>;
+				reg-names = "dsi_phy",
+					    "dsi_phy_lane",
+					    "dsi_pll";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+					 <&rpmhcc RPMH_CXO_CLK>;
+				clock-names = "iface", "ref";
+
+				status = "disabled";
+			};
+
+			mdss1_dsi1: dsi@22096000 {
+				compatible = "qcom,sc8280xp-dsi-ctrl",
+					     "qcom,sa8775p-dsi-ctrl",
+					     "qcom,mdss-dsi-ctrl";
+				reg = <0 0x22096000 0 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss1>;
+				interrupts = <5>;
+
+				clocks = <&dispcc1 DISP_CC_MDSS_BYTE1_CLK>,
+					 <&dispcc1 DISP_CC_MDSS_BYTE1_INTF_CLK>,
+					 <&dispcc1 DISP_CC_MDSS_PCLK1_CLK>,
+					 <&dispcc1 DISP_CC_MDSS_ESC1_CLK>,
+					 <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+					 <&gcc GCC_DISP_HF_AXI_CLK>;
+				clock-names = "byte",
+					      "byte_intf",
+					      "pixel",
+					      "core",
+					      "iface",
+					      "bus";
+
+				assigned-clocks = <&dispcc1 DISP_CC_MDSS_BYTE1_CLK_SRC>,
+						  <&dispcc1 DISP_CC_MDSS_PCLK1_CLK_SRC>;
+				assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>,
+							 <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>;
+
+				operating-points-v2 = <&dsi_opp_table>;
+				power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+				refgen-supply = <&refgen>;
+
+				phys = <&mdss1_dsi1_phy>;
+				phy-names = "dsi";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdss1_dsi1_in: endpoint {
+							remote-endpoint = <&mdss1_intf2_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						mdss1_dsi1_out: endpoint {
+						};
+					};
+				};
+			};
+
+			mdss1_dsi1_phy: phy@22096400 {
+				compatible = "qcom,sc8280xp-dsi-phy-5nm",
+					     "qcom,sa8775p-dsi-phy-5nm";
+				reg = <0 0x22096400 0 0x200>,
+				      <0 0x22096600 0 0x280>,
+				      <0 0x22096900 0 0x280>;
+				reg-names = "dsi_phy",
+					    "dsi_phy_lane",
+					    "dsi_pll";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
+					 <&rpmhcc RPMH_CXO_CLK>;
+				clock-names = "iface", "ref";
+
+				status = "disabled";
+			};
+
 			mdss1_dp1: displayport-controller@22098000 {
 				compatible = "qcom,sc8280xp-dp";
 				reg = <0 0x22098000 0 0x200>,
@@ -6434,10 +6822,10 @@ dispcc1: clock-controller@22100000 {
 				 <&mdss1_dp2_phy 1>,
 				 <&mdss1_dp3_phy 0>,
 				 <&mdss1_dp3_phy 1>,
-				 <0>,
-				 <0>,
-				 <0>,
-				 <0>;
+				 <&mdss1_dsi0_phy DSI_BYTE_PLL_CLK>,
+				 <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>,
+				 <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>,
+				 <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>;
 			power-domains = <&rpmhpd SC8280XP_MMCX>;
 
 			#clock-cells = <1>;
-- 
2.53.0

Claude review: Add DSI display support for SC8280XP

[Claude Code Review Bot]

Overall Series Review

Subject: Add DSI display support for SC8280XP
Author: Pengyu Luo <mitltlatltl@gmail.com>
Patches: 5
Reviewed: 2026-03-09T07:56:45.643189

---

This is a clean, well-structured v4 series adding DSI display support for the SC8280XP SoC. It follows standard Qualcomm DT patterns: first adding binding compatibles (patches 1-2), then documenting the MDSS schema (patch 3), and finally the DTS nodes (patch 4). The series correctly falls back to SA8775P compatibles for both the DSI controller and PHY. All three binding patches already carry `Reviewed-by` from Krzysztof Kozlowski, and patch 4 has reviews from Dmitry Baryshkov and Konrad Dybcio.

**There is one likely copy-paste bug in patch 4** in the `mdss1_dsi0` node's `assigned-clock-parents` that should be addressed before merging.

---
Generated by Claude Code Patch Reviewer

Claude review: dt-bindings: display: msm-dsi-phy-7nm: Add SC8280XP

[Claude Code Review Bot]

Patch Review

Straightforward one-line addition adding `qcom,sc8280xp-dsi-phy-5nm` as a fallback to `qcom,sa8775p-dsi-phy-5nm`. Correctly placed in alphabetical order next to the existing `qcom,qcs8300-dsi-phy-5nm` entry.

No issues.

---
Generated by Claude Code Patch Reviewer

Claude review: dt-bindings: display/msm: dsi-controller-main: Add SC8280XP

[Claude Code Review Bot]

Patch Review

Same pattern as patch 1, adding `qcom,sc8280xp-dsi-ctrl` falling back to `qcom,sa8775p-dsi-ctrl` and then `qcom,mdss-dsi-ctrl`. Correctly placed alphabetically.

No issues.

---
Generated by Claude Code Patch Reviewer

Claude review: dt-bindings: display: msm: Document DSI controller and DSI PHY on SC8280XP

[Claude Code Review Bot]

Patch Review

Adds `dsi@` and `phy@` pattern properties to the sc8280xp-mdss schema, plus example port entries for `port@1` and `port@2` connecting to the DSI endpoints.

No issues. The schema additions follow the same pattern used by other MDSS bindings.

---
Generated by Claude Code Patch Reviewer

Claude review: arm64: dts: qcom: sc8280xp: Add dsi nodes on SC8280XP

[Claude Code Review Bot]

Patch Review

This is the main patch, adding 4 DSI controllers (2 per MDSS) and 4 DSI PHYs, plus wiring up the dispcc clock inputs and DPU output ports.

**Bug: `mdss1_dsi0` has mismatched `assigned-clock-parents`**

At lines 1054-1055 of the mbox (corresponding to sc8280xp.dtsi lines 6399-6400):

```dts
assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>,
                         <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>;
```

The byte clock parent references `mdss1_dsi1_phy` but the pixel clock parent references `mdss1_dsi0_phy`. Comparing with all other DSI controller nodes in this patch:

- `mdss0_dsi0`: both from `mdss0_dsi0_phy` (consistent)
- `mdss0_dsi1`: both from `mdss0_dsi1_phy` (consistent)
- `mdss1_dsi1`: both from `mdss1_dsi1_phy` (consistent)
- `mdss1_dsi0`: **byte from `mdss1_dsi1_phy`, pixel from `mdss1_dsi0_phy`** (inconsistent)

This is almost certainly a copy-paste error. The byte clock parent should be `mdss1_dsi0_phy`, not `mdss1_dsi1_phy`:

```dts
assigned-clock-parents = <&mdss1_dsi0_phy DSI_BYTE_PLL_CLK>,
                         <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>;
```

**Other observations (non-blocking):**

- The `dsi_opp_table` is defined inside `mdss0_dsi0` and referenced by all four DSI controllers including the mdss1 ones. This is a valid approach via phandle cross-referencing and was explicitly requested by Konrad in v2 review. It works but is slightly unusual to have mdss1 nodes reference a table nested inside an mdss0 child.
- The commit message honestly notes that "DSI won't work properly for now until we submit dispcc fixes" - this is good transparency, and the nodes default to `status = "disabled"`.
- The whitespace-only changes (adding blank lines between `reg` property and label in existing `port@` nodes) are reasonable DT style cleanup.
- The `#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>` is correct despite the "28nm" in the name - this header simply defines the generic `DSI_BYTE_PLL_CLK`/`DSI_PIXEL_PLL_CLK` indices used across all DSI PHY generations.

---
Generated by Claude Code Patch Reviewer