Claude review: arm64: dts: qcom: glymur: Add ADSP and CDSP for Glymur SoC

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

This is the main DTS patch adding 286 lines to `glymur.dtsi`. Key observations:

**ADSP node** (`remoteproc@6800000`):
- Compatible: `"qcom,glymur-adsp-pas", "qcom,sm8550-adsp-pas"` — matches binding.
- 6 interrupts including "shutdown-ack" — matches the binding's maxItems: 6 conditional.
- Power domains: `lcx`, `lmx` — matches the sm8550-adsp-pas power domain constraint.
- IOMMU: `<&apps_smmu 0x1000 0x0>` — optional per cover letter, present here.
- Fastrpc compute CBs 3-8 with dual IOMMU entries and `dma-coherent` — consistent pattern.
- CB 7 has three IOMMU entries with different masks (`0x40`, `0x0`, `0x0`) versus the other CBs (`0x80`, `0x20`) — this is likely intentional as a secure/non-secure split.

**CDSP node** (`remoteproc@32300000`):
- Compatible: `"qcom,glymur-cdsp-pas", "qcom,sm8550-cdsp-pas"` — matches binding.
- 6 interrupts including "shutdown-ack" — matches binding.
- Power domains: `cx`, `mxc`, `nsp` (3 domains) — matches the sm8550-cdsp-pas constraint.
- Fastrpc compute CBs 1-8, 10-12 with CB 9 documented as secure:
```c
					/* note: compute-cb@9 is secure */
```
- The SID gap from 0x2408 (CB 8) to 0x240c (CB 10) accounts for 3 secure CBs in the SID space (0x2409–0x240b), which is a standard Qualcomm CDSP IOMMU layout.

Both nodes have `status = "disabled"` as expected for SoC-level dtsi.

No issues. Reviewed-by from both Abel Vesa and Konrad Dybcio.

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Generated by Claude Code Patch Reviewer