From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: phy: qualcomm: add MSM8974 HDMI PHY support
Date: Mon, 16 Mar 2026 12:08:00 +1000 [thread overview]
Message-ID: <review-patch4-20260314-fd-hdmi-phy-v5-4-58122ae96d3b@oss.qualcomm.com> (raw)
In-Reply-To: <20260314-fd-hdmi-phy-v5-4-58122ae96d3b@oss.qualcomm.com>
Patch Review
Adds PLL programming and rate calculation for the MSM8974 HDMI PHY, building on the infrastructure from patch 1 and the UNI PLL registers from patches 2-3.
**Comparison bug in `qcom_hdmi_msm8974_phy_pll_set_rate`:**
```c
+ if (pixclk == 297000) {
+ hdmi_phy_write(hdmi_phy, REG_HDMI_8x74_ANA_CFG2, 0x06);
+ hdmi_phy_write(hdmi_phy, REG_HDMI_8x74_ANA_CFG3, 0x03);
+ } else if (pixclk == 268500) {
```
`pixclk` is `hdmi_phy->hdmi_opts.tmds_char_rate` which is in Hz (e.g., 297000000), but the comparisons use kHz values (297000, 268500). These comparisons will never match. This should be either `297000000` / `268500000`, or `pixclk` should be divided by 1000 first. This is a functional bug.
**`qcom_uniphy_recalc` — refclk_div calculation:**
```c
+ rate *= (refclk_cfg >> 2) * 0x3 + 1;
```
The mask `0x3` applied after shifting right by 2 extracts bits [3:2] of refclk_cfg. But looking at the setup code:
```c
+ val = (ref_freq_mult_2 ? BIT(0) : 0) |
+ ((refclk_div - 1) << 2);
```
The divider is stored in bits [3:2] as `(refclk_div - 1)`. The recalc multiplies by `(field & 0x3) + 1` which correctly recovers `refclk_div`. However, `0x3` should probably be written as a proper mask. The expression `* 0x3` specifically reads oddly — it looks like it's multiplying by 3 rather than ANDing. It's actually `& 0x3` implicitly due to being the full 2-bit field. Wait, re-reading: `(refclk_cfg >> 2) * 0x3 + 1` — this is `(field_value * 3) + 1`, not `(field_value & 3) + 1`. For `refclk_div=1`, stored as 0, this gives `0*3+1 = 1` (correct). For other values this seems wrong. This looks like it should be `((refclk_cfg >> 2) & 0x3) + 1`. This is another potential bug.
**Missing `Reviewed-by` for patch 4:** Unlike patches 2 and 3 which have Neil Armstrong's Reviewed-by, this patch does not. Being the most complex new patch, it would benefit from additional review.
Overall this is a well-executed series with a few bugs that need fixing before merging, particularly the missing compatibles (8084, 8998), the pixclk unit mismatch in patch 4, and the suspicious recalc formula.
---
Generated by Claude Code Patch Reviewer
next prev parent reply other threads:[~2026-03-16 2:08 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-14 5:06 [PATCH v5 0/4] drm/msm/hdmi & phy: use generic PHY framework Dmitry Baryshkov
2026-03-14 5:06 ` [PATCH v5 1/4] drm/msm/hdmi: switch to generic PHY subsystem Dmitry Baryshkov
2026-03-16 2:07 ` Claude review: " Claude Code Review Bot
2026-03-14 5:06 ` [PATCH v5 2/4] phy: qcom: apq8064-sata: extract UNI PLL register defines Dmitry Baryshkov
2026-03-16 2:07 ` Claude review: " Claude Code Review Bot
2026-03-14 5:06 ` [PATCH v5 3/4] phy: qcom-uniphy: add more registers from display PHYs Dmitry Baryshkov
2026-03-16 2:07 ` Claude review: " Claude Code Review Bot
2026-03-14 5:06 ` [PATCH v5 4/4] phy: qualcomm: add MSM8974 HDMI PHY support Dmitry Baryshkov
2026-03-16 2:08 ` Claude Code Review Bot [this message]
2026-03-16 2:07 ` Claude review: drm/msm/hdmi & phy: use generic PHY framework Claude Code Review Bot
-- strict thread matches above, loose matches on Subject: below --
2026-03-19 3:48 [PATCH v6 0/4] " Dmitry Baryshkov
2026-03-19 3:48 ` [PATCH v6 4/4] phy: qualcomm: add MSM8974 HDMI PHY support Dmitry Baryshkov
2026-03-21 18:56 ` Claude review: " Claude Code Review Bot
2026-03-23 22:56 [PATCH v7 0/4] drm/msm/hdmi & phy: use generic PHY framework Dmitry Baryshkov
2026-03-23 22:56 ` [PATCH v7 4/4] phy: qualcomm: add MSM8974 HDMI PHY support Dmitry Baryshkov
2026-03-24 21:14 ` Claude review: " Claude Code Review Bot
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