Claude review: drm/msm/dpu: fix video mode DSC INTF timing width calculation

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**This is the most interesting patch and the fix looks correct.**

The old code:
```c
timing->width = timing->width * drm_dsc_get_bpp_int(dsc) /
                (dsc->bits_per_component * 3);
```

For 8-bit panels: `8 * 3 = 24` — works correctly.
For 10-bit panels: `10 * 3 = 30` — produces the wrong divisor, causing FIFO errors.

The fix:
```c
timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / 24;
```

The reasoning is that DSI always transfers 24 bits of compressed data per pixel clock, regardless of source pixel depth. The compression ratio is already captured by `drm_dsc_get_bpp_int(dsc)` — the divisor represents the interface transfer width, not the source bit depth.

**This should have a `Fixes:` tag** since it fixes commit that originally added this DSC timing calculation. Without it, stable backport won't pick this up. The commit that introduced this formula should be identified and referenced.

The updated comment is clearer than the original:
```c
+	 * For DSI, if DSC is enabled, 24 bits of compressed data are
+	 * transferred per pclk regardless of the source pixel depth.
```

This is a real bug fix that would affect any non-8bpc DSC panel, independent of the RGB101010 format support.

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Generated by Claude Code Patch Reviewer