From mboxrd@z Thu Jan  1 00:00:00 1970
From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/msm/dpu: fix video mode DSC INTF timing width calculation
Date: Sun, 22 Mar 2026 04:21:57 +1000
Message-ID: <review-patch4-20260319-dsi-rgb101010-support-v3-4-85b99df2d090@pm.me>
In-Reply-To: <20260319-dsi-rgb101010-support-v3-4-85b99df2d090@pm.me>
References: <20260319-dsi-rgb101010-support-v3-0-85b99df2d090@pm.me> <20260319-dsi-rgb101010-support-v3-4-85b99df2d090@pm.me>
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Patch Review

**This is the most interesting patch and the fix looks correct.**

The old code:
```c
timing->width =3D timing->width * drm_dsc_get_bpp_int(dsc) /
                (dsc->bits_per_component * 3);
```

For 8-bit panels: `8 * 3 =3D 24` =E2=80=94 works correctly.
For 10-bit panels: `10 * 3 =3D 30` =E2=80=94 produces the wrong divisor, ca=
using FIFO errors.

The fix:
```c
timing->width =3D timing->width * drm_dsc_get_bpp_int(dsc) / 24;
```

The reasoning is that DSI always transfers 24 bits of compressed data per p=
ixel clock, regardless of source pixel depth. The compression ratio is alre=
ady captured by `drm_dsc_get_bpp_int(dsc)` =E2=80=94 the divisor represents=
 the interface transfer width, not the source bit depth.

**This should have a `Fixes:` tag** since it fixes commit that originally a=
dded this DSC timing calculation. Without it, stable backport won't pick th=
is up. The commit that introduced this formula should be identified and ref=
erenced.

The updated comment is clearer than the original:
```c
+	 * For DSI, if DSC is enabled, 24 bits of compressed data are
+	 * transferred per pclk regardless of the source pixel depth.
```

This is a real bug fix that would affect any non-8bpc DSC panel, independen=
t of the RGB101010 format support.

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