Claude review: drm/amd/display: Implement deferred vblanks on IPS platforms

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**1. `active_vblank_irq_count` is not protected**

```c
dm->active_vblank_irq_count++;
```

This counter is incremented/decremented in the deferred callbacks, which run in workqueue context. Without any lock protecting it, concurrent enable/disable on different CRTCs could race. The deferred workqueue isn't ordered (see patch 2 review), so these can run in parallel.

**2. `dc_lock` held across pre→enable→post boundary is asymmetric**

`pre_enable_vblank` acquires `dc_lock`, and `post_enable_vblank` releases it. This means the DRM vblank core's `drm_vblank_enable()` (called between pre and post) runs with `dc_lock` held. This works for the IPS use case, but it means the `enable_vblank` driver callback also runs with `dc_lock` held — which is the intent, but it couples the DRM core's locking guarantees to driver-internal lock ordering. If any code path under `drm_vblank_enable()` ever tries to acquire a lock that `dc_lock` nests inside, it would deadlock.

**3. Accessing `crtc->state` without proper locking**

```c
struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
```

In `post_enable_vblank` and `post_disable_vblank`, `crtc->state` is accessed from workqueue context. The `crtc->state` pointer can change during atomic commits. This needs either atomic state locking or the driver needs to ensure the state won't change while the worker runs (e.g., by holding a reference or ensuring commit serialization). This is a pre-existing pattern in the AMDGPU driver's vblank control worker, but deferring it to the DRM core's workqueue may change timing assumptions.

**4. `vblank_control_work` on the stack**

```c
struct vblank_control_work vblank_work = { 0 };
```

Using a stack-allocated `vblank_control_work` and calling `amdgpu_dm_crtc_set_panel_sr_feature()` with it seems fine as long as that function doesn't store a pointer to it. Worth verifying.

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