From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/dp: Add DPCD for configuring AS SDP for PR + VRR Date: Tue, 31 Mar 2026 17:39:45 +1000 Message-ID: In-Reply-To: <20260330040656.4116502-5-ankit.k.nautiyal@intel.com> References: <20260330040656.4116502-1-ankit.k.nautiyal@intel.com> <20260330040656.4116502-5-ankit.k.nautiyal@intel.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Issue: The DPCD address 0x11a for `PANEL_REPLAY_CONFIG3` doesn't look rig= ht.** The existing `PANEL_REPLAY_CONFIG` is at 0x1b0 and `PANEL_REPLAY_CONF= IG2` is at 0x1b1. Address 0x11a is in a different DPCD region entirely (nea= r the payload allocation area at 0x1c0). Patch 15 then does a 3-byte burst = write starting at `PANEL_REPLAY_CONFIG` (0x1b0), which would write to 0x1b0= , 0x1b1, and 0x1b2 =E2=80=94 not 0x11a. Either: - The address 0x11a is wrong and should be 0x1b2, or - The burst write in patch 15 is wrong This needs clarification against the DP 2.1 spec. No R-b tag on this patch. ```c +#define PANEL_REPLAY_CONFIG3 0x11a /* DP 2.1 */ ``` --- Generated by Claude Code Patch Reviewer