From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/adreno: set cx_misc_mmio regardless of if platform has LLCC Date: Sun, 12 Apr 2026 13:17:01 +1000 Message-ID: In-Reply-To: <20260407-adreno-810-v3-4-30cb7f196ed4@pm.me> References: <20260407-adreno-810-v3-0-30cb7f196ed4@pm.me> <20260407-adreno-810-v3-4-30cb7f196ed4@pm.me> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review This patch decouples the `cx_misc_mmio` mapping from LLCC slice availabilit= y. The key motivation is that Milos has no LLCC but still needs access to C= X_MISC registers (for TCM retention, software fuses, etc.). The approach is sound: - MMU500 detection and `cx_misc_mmio` mapping are moved from `a6xx_llc_slic= es_init()` into `a6xx_gpu_init()`. - The early-return guards in `a6xx_llc_activate()` and `a7xx_llc_activate()= ` are changed from checking `cx_misc_mmio` to checking whether LLC slices a= re available directly: ```c - if (IS_ERR(a6xx_gpu->cx_misc_mmio)) + if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) ``` This is safe because `a7xx_llc_activate()` (the path used for A8xx) does no= t use `cx_misc_mmio` =E2=80=94 it only writes GPU registers via `gpu_write(= )` and calls `llcc_slice_activate()`. The `a6xx_llc_activate()` path does u= se `cx_misc_mmio` but only inside the `if (!a6xx_gpu->have_mmu500)` block, = and for platforms that reach that code, `cx_misc_mmio` will be mapped (sinc= e `!have_mmu500` is one of the conditions for mapping it). Already has Reviewed-by from both Konrad Dybcio and Akhil P Oommen. Looks c= orrect. --- Generated by Claude Code Patch Reviewer