From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: arm64: dts: qcom: glymur: Add GPU smmu node Date: Sat, 16 May 2026 14:42:43 +1000 Message-ID: In-Reply-To: <20260512-glymur-gpu-dt-v3-4-84232dc21c03@oss.qualcomm.com> References: <20260512-glymur-gpu-dt-v3-0-84232dc21c03@oss.qualcomm.com> <20260512-glymur-gpu-dt-v3-4-84232dc21c03@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review **Change:** Adds the `adreno_smmu: iommu@3da0000` node to glymur.dtsi. The node follows the standard pattern for Qualcomm GPU SMMUs: - Compatible: `"qcom,glymur-smmu-500", "qcom,adreno-smmu", "qcom,smmu-500", "arm,mmu-500"` (4-element chain as required by the binding) - 1 global interrupt + 25 context bank interrupts (26 total, `#global-interrupts = <1>`) - Single `hlos` clock from gpucc - `power-domains` referencing CX GDSC - `dma-coherent` present The node is placed after `gpucc` and before `ipcc` -- address ordering is correct (0x3da0000 between 0x3d90000 and 0x3e04000). **Verdict:** Looks clean. Already has Reviewed-by from Konrad and Dmitry. --- --- Generated by Claude Code Patch Reviewer