From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/bridge: tc358762: Configure SYSCTRL first Date: Sat, 16 May 2026 12:04:22 +1000 Message-ID: In-Reply-To: <20260513-tc358762-fixes-v3-4-6698b55008b9@ideasonboard.com> References: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> <20260513-tc358762-fixes-v3-4-6698b55008b9@ideasonboard.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review Moves the SYSCTRL write (which configures DPI I/O drive strength and pixel = clock divider) to the beginning of `tc358762_init()`, before enabling DSI l= anes and DPI output. This is sensible =E2=80=94 the clock tree and I/O shou= ld be configured before enabling downstream blocks. The `msleep(100)` moves with it, which makes sense as it likely gives the P= LL/clock divider time to stabilize. No issues. **Reviewed-by worthy.** --- Generated by Claude Code Patch Reviewer