From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/adreno: set cx_misc_mmio regardless of if platform has LLCC Date: Sat, 16 May 2026 10:05:41 +1000 Message-ID: In-Reply-To: <20260515-adreno-810-v6-4-fbe04c7203e1@pm.me> References: <20260515-adreno-810-v6-0-fbe04c7203e1@pm.me> <20260515-adreno-810-v6-4-fbe04c7203e1@pm.me> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review **Status: Mostly good, one concern** This patch decouples `cx_misc_mmio` mapping from LLCC slice availability. The motivation is clear: Milos has no LLCC but still needs to access `cx_mem` for fuse reads, TCM retention control, etc. Previously, if LLCC slices were unavailable, `cx_misc_mmio` was overwritten with `ERR_PTR(-EINVAL)`. The approach is to: 1. Move MMU500 detection and `cx_misc_mmio` mapping from `a6xx_llc_slices_init()` into `a6xx_gpu_init()` 2. Change the early-return guard in `a6xx_llc_activate()` and `a7xx_llc_activate()` from checking `cx_misc_mmio` to checking both LLC slices directly **Concern**: After this patch, if `cx_misc_mmio` mapping fails (msm_ioremap returns ERR_PTR) but LLCC slices succeed, the LLC activate functions would proceed to dereference an invalid `cx_misc_mmio` pointer via `a6xx_cx_misc_write()`/`a6xx_cx_misc_rmw()`. In practice this is unlikely (a platform with LLCC would have cx_mem), but the original code was more defensive by using `cx_misc_mmio` validity as the gatekeeper. Consider adding a check for `IS_ERR_OR_NULL(a6xx_gpu->cx_misc_mmio)` in the activate paths, or at least in `a6xx_gpu_init()` after the mapping. --- Generated by Claude Code Patch Reviewer