From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: arm64: dts: qcom: Add GPU support for Glymur Date: Mon, 25 May 2026 18:58:50 +1000 Message-ID: In-Reply-To: <20260522-glymur-gpu-dt-v5-4-562c406b210c@oss.qualcomm.com> References: <20260522-glymur-gpu-dt-v5-0-562c406b210c@oss.qualcomm.com> <20260522-glymur-gpu-dt-v5-4-562c406b210c@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Summary:** Adds the GPU and GMU DT nodes with OPP tables, interconnects, = and IOMMU references. The GPU node at `0x3d00000` (size `0x6c000`) and GMU at `0x3d6c000` (size `= 0x32000`) are contiguous and non-overlapping: - GPU: `0x3d00000` =E2=80=93 `0x3d6bfff` - GMU: `0x3d6c000` =E2=80=93 `0x3d9dfff` - cx_mem: `0x3d9e000` =E2=80=93 `0x3d9ffff` The RSCC at `gpu_base + 0x50000 =3D 0x3d50000` falls within the GPU kgsl_3d= 0_reg_memory range, consistent with patch 1. The GPU OPP table has 12 entries ranging from 310 MHz to 1850 MHz (the cove= r letter's claimed max Fmax). The higher OPPs (1550+ MHz) use `opp-supporte= d-hw =3D <0x7>` and `<0x3>` to restrict to specific speedbins =E2=80=94 thi= s is standard practice. The GMU OPP table has 4 entries (575=E2=80=93750 MHz), which is reasonable. **Observation:** The GMU register range (`0x3d6c000`, size `0x32000`, endin= g at `0x3d9dfff`) overlaps with `gpucc` at `0x3d90000` (size `0x9800`). Thi= s is likely intentional =E2=80=94 the GMU driver only accesses its own regi= sters within this range, and the clock controller has a separate ioremap. T= his pattern appears in other Qualcomm SoCs. Mentioned for completeness only. Already has Reviewed-by from Konrad Dybcio. No blocking issues. --- Generated by Claude Code Patch Reviewer