From mboxrd@z Thu Jan  1 00:00:00 1970
From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/tyr: add MMU address space registers
Date: Tue, 03 Mar 2026 12:48:19 +1000
Message-ID: <review-patch5-20260302232500.244489-6-deborah.brouwer@collabora.com>
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Patch Review

**Author:** Daniel Almeida

Adds register definitions and an `AsRegister` helper for per-address-space =
register access.

One concern: `AsRegister::new()` does not validate `as_nr`:

```rust
+impl AsRegister {
+    fn new(as_nr: usize, offset: usize) -> Result<Self> {
+        Ok(AsRegister(mmu_as(as_nr) + offset))
+    }
```

It returns `Result` but never returns an error. If `as_nr >=3D MAX_AS_REGIS=
TERS`, the computed offset will be out of the expected MMIO range. While ca=
llers in the address_space module do call `validate_as_slot()` before using=
 these registers, the validation is in `AsRegister::new` is misleading sinc=
e it always succeeds. Consider either adding a bounds check here or changin=
g the return type to plain `AsRegister` (not `Result`). Given the `try_read=
32`/`try_write32` calls in read/write will catch truly out-of-bounds access=
es at the IoMem level, this is a defense-in-depth concern rather than a fun=
ctional bug.

Minor nit: `AS_MEMATTR_AARCH64_SH_MIDGARD_INNER` is `0 << 4` which is just =
`0`. A comment noting this is intentional (the zero value selects "midgard =
inner" shareability) would improve readability.

The change from `MAX_AS_REGISTERS =3D 32` to `16` matches the Mali CSF spec=
 =E2=80=94 good fix.

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