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From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: gpu: host1x: convert MIPI to use operation function pointers
Date: Wed, 04 Mar 2026 07:48:06 +1000	[thread overview]
Message-ID: <review-patch5-20260303084239.15007-6-clamor95@gmail.com> (raw)
In-Reply-To: <20260303084239.15007-6-clamor95@gmail.com>

Patch Review

This is the large refactoring patch that introduces the `tegra_mipi_ops` abstraction, creates `tegra114-mipi.c` with the Tegra114+ calibration logic, and establishes the provider model via `devm_tegra_mipi_add_provider()`.

**Bug: clock leak in `tegra114_mipi_power_down()`:**

```c
static int tegra114_mipi_power_down(struct tegra_mipi *mipi)
{
	u32 value;
	int err;

	err = clk_enable(mipi->clk);
	if (err < 0)
		return err;
	...
	value |= MIPI_CAL_BIAS_PAD_PDVCLAMP;
	tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0);

	return 0;  // <-- missing clk_disable(mipi->clk)
}
```

`clk_enable()` is called at the top but `clk_disable()` is never called before returning. Compare with `tegra114_mipi_power_up()` which does correctly call `clk_disable()`. This will leak a clock enable count on every power-down.

**Minor: Duplicate defines with same register offset.** `MIPI_CAL_CONFIG_DSIC_CLK` and `MIPI_CAL_CONFIG_CSICD_CLK` are both `0x1c`, and `MIPI_CAL_CONFIG_DSID_CLK` and `MIPI_CAL_CONFIG_CSIE_CLK` are both `0x1d`. This is intentional (shared hardware registers), but a comment would be helpful for clarity.

---
Generated by Claude Code Patch Reviewer

  reply	other threads:[~2026-03-03 21:48 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-03  8:42 [PATCH v7 00/15] tegra-video: add CSI support for Tegra20 and Tegra30 Svyatoslav Ryhel
2026-03-03  8:42 ` [PATCH v7 01/15] staging: media: tegra-video: expand VI and VIP support to Tegra30 Svyatoslav Ryhel
2026-03-03 21:48   ` Claude review: " Claude Code Review Bot
2026-03-03  8:42 ` [PATCH v7 02/15] staging: media: tegra-video: vi: adjust get_selection operation check Svyatoslav Ryhel
2026-03-03 21:48   ` Claude review: " Claude Code Review Bot
2026-03-03  8:42 ` [PATCH v7 03/15] staging: media: tegra-video: vi: add flip controls only if no source controls are provided Svyatoslav Ryhel
2026-03-03 21:48   ` Claude review: " Claude Code Review Bot
2026-03-03  8:42 ` [PATCH v7 04/15] staging: media: tegra-video: csi: move CSI helpers to header Svyatoslav Ryhel
2026-03-03 21:48   ` Claude review: " Claude Code Review Bot
2026-03-03  8:42 ` [PATCH v7 05/15] gpu: host1x: convert MIPI to use operation function pointers Svyatoslav Ryhel
2026-03-03 21:48   ` Claude Code Review Bot [this message]
2026-03-03  8:42 ` [PATCH v7 06/15] staging: media: tegra-video: vi: improve logic of source requesting Svyatoslav Ryhel
2026-03-03 21:48   ` Claude review: " Claude Code Review Bot
2026-03-03  8:42 ` [PATCH v7 07/15] staging: media: tegra-video: csi: move avdd-dsi-csi-supply from VI to CSI Svyatoslav Ryhel
2026-03-03 21:48   ` Claude review: " Claude Code Review Bot
2026-03-03  8:42 ` [PATCH v7 08/15] staging: media: tegra-video: tegra20: set correct maximum width and height Svyatoslav Ryhel
2026-03-03 21:48   ` Claude review: " Claude Code Review Bot
2026-03-03  8:42 ` [PATCH v7 09/15] staging: media: tegra-video: tegra20: add support for second output of VI Svyatoslav Ryhel
2026-03-03 21:48   ` Claude review: " Claude Code Review Bot
2026-03-03  8:42 ` [PATCH v7 10/15] staging: media: tegra-video: tegra20: adjust format align calculations Svyatoslav Ryhel
2026-03-03 21:48   ` Claude review: " Claude Code Review Bot
2026-03-03  8:42 ` [PATCH v7 11/15] staging: media: tegra-video: tegra20: set VI HW revision Svyatoslav Ryhel
2026-03-03 21:48   ` Claude review: " Claude Code Review Bot
2026-03-03  8:42 ` [PATCH v7 12/15] staging: media: tegra-video: tegra20: increase maximum VI clock frequency Svyatoslav Ryhel
2026-03-03 21:48   ` Claude review: " Claude Code Review Bot
2026-03-03  8:42 ` [PATCH v7 13/15] staging: media: tegra-video: tegra20: expand format support with RAW8/10 and YUV422/YUV420p 1X16 Svyatoslav Ryhel
2026-03-03 21:48   ` Claude review: " Claude Code Review Bot
2026-03-03  8:42 ` [PATCH v7 14/15] staging: media: tegra-video: tegra20: adjust luma buffer stride Svyatoslav Ryhel
2026-03-03 21:48   ` Claude review: " Claude Code Review Bot
2026-03-03  8:42 ` [PATCH v7 15/15] staging: media: tegra-video: add CSI support for Tegra20 and Tegra30 Svyatoslav Ryhel
2026-03-03 21:48   ` Claude review: " Claude Code Review Bot
2026-03-03 21:48 ` Claude review: " Claude Code Review Bot

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