From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/panthor: Use a local iomem base for GPU registers Date: Sun, 12 Apr 2026 09:38:16 +1000 Message-ID: In-Reply-To: <20260410164637.549145-6-karunika.choo@arm.com> References: <20260410164637.549145-1-karunika.choo@arm.com> <20260410164637.549145-6-karunika.choo@arm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review The `GPU_CONTROL_BASE` is defined as `0x0`, which is technically correct (GPU registers do start at offset 0) but `gpu->iomem = ptdev->iomem + GPU_CONTROL_BASE` is equivalent to `gpu->iomem = ptdev->iomem`. This adds a level of indirection without actually changing the base pointer. It's fine as documentation/consistency but is somewhat unusual. The conversion of `panthor_gpu_irq_handler` to use `gpu->irq.iomem` for `INT_CLEAR` and `gpu->iomem` for fault/status registers is correct. The `panthor_gpu_flush_caches` and `panthor_gpu_soft_reset` correctly use `gpu->irq.iomem` for `INT_RAWSTAT` and `INT_CLEAR` reads. The removal of the absolute `GPU_INT_RAWSTAT`/`GPU_INT_CLEAR`/etc. defines from `panthor_gpu_regs.h` is correct since all accesses now go through the generic `INT_*` offsets via `pirq->iomem`. No issues in this patch. --- Generated by Claude Code Patch Reviewer