From mboxrd@z Thu Jan  1 00:00:00 1970
From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/panthor: Use a local iomem base for GPU registers
Date: Mon, 13 Apr 2026 19:05:52 +1000
Message-ID: <review-patch5-20260412142951.2309135-6-karunika.choo@arm.com>
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Patch Review

**Status: Good.**

Adds `void __iomem *iomem` to `struct panthor_gpu`, initialized to `ptdev->=
iomem + GPU_CONTROL_BASE` (offset 0x0, so identical to `ptdev->iomem`):

```c
+	gpu->iomem =3D ptdev->iomem + GPU_CONTROL_BASE;
```

All GPU register accesses switch from `gpu_read(ptdev->iomem, GPU_XXX)` to =
`gpu_read(gpu->iomem, GPU_XXX)`. Since `GPU_CONTROL_BASE` is 0x0, the regis=
ter defines don't need rebasing =E2=80=94 they retain their existing values.

For IRQ, the GPU_INT registers are at offset 0x1000 (`GPU_INT_BASE`), so th=
e IRQ iomem is set to:
```c
+	ret =3D panthor_request_gpu_irq(ptdev, ptdev->iomem + GPU_INT_BASE, ...);
```

The `GPU_INT_RAWSTAT`, `GPU_INT_CLEAR`, `GPU_INT_MASK`, `GPU_INT_STAT` defi=
nes are removed since they're now handled via the generic `INT_*` offsets r=
elative to the IRQ's iomem base. Correct.

In `panthor_hw.c`, a local variable is introduced since `panthor_hw.c` does=
n't have direct access to the `panthor_gpu` struct internals:
```c
+	void __iomem *gpu_iomem =3D ptdev->iomem + GPU_CONTROL_BASE;
```

This is clean.

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