From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: arm64: dts: qcom: Add GPU support for Glymur Date: Sat, 16 May 2026 14:42:43 +1000 Message-ID: In-Reply-To: <20260512-glymur-gpu-dt-v3-5-84232dc21c03@oss.qualcomm.com> References: <20260512-glymur-gpu-dt-v3-0-84232dc21c03@oss.qualcomm.com> <20260512-glymur-gpu-dt-v3-5-84232dc21c03@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review **Change:** Adds the `gpu@3d00000` and `gmu@3d6c000` nodes to glymur.dtsi. **GPU node (`gpu@3d00000`):** - Compatible: `"qcom,adreno-44070001", "qcom,adreno"` -- matches catalog - reg: `kgsl_3d0_reg_memory` at 0x3d00000 size 0x6c000, `cx_mem` at 0x3d9e000 size 0x2000 -- matches the 2-reg constraint from patch 2 - The kgsl_3d0_reg_memory range (0x3d00000 - 0x3d6c000) encompasses the RSCC at 0x3d50000 (gpu base + 0x50000 from patch 1), which is consistent - 12 OPP entries from 310MHz to 1850MHz, with ACD disabled on the two lowest frequencies - The highest OPPs (1550/1700/1850 MHz) have progressively restricted `opp-supported-hw` masks (0x7, 0x7, 0x3), consistent with speedbin support in the catalog - interconnects properly reference `hsc_noc` and `mc_virt` **GMU node (`gmu@3d6c000`):** - Compatible: `"qcom,adreno-gmu-x285.1", "qcom,adreno-gmu"` - reg: single "gmu" region at 0x3d6c000, size 0x32000 - 6 clocks including `rscc` clock -- note this is a new clock compared to some other GMU nodes - Power domains: CX from gpucc, GX from gxclkctl - 4 GMU OPP entries from 575MHz to 750MHz **Node ordering:** `gpu@3d00000` is inserted before `gxclkctl@3d64000`, and `gmu@3d6c000` is inserted after `gxclkctl` and before `gpucc@3d90000`. This maintains ascending address order. **Address overlap note:** The GPU kgsl_3d0_reg_memory range (0x3d00000-0x3d6c000) physically encompasses the gxclkctl range (0x3d64000-0x3d6a000). Similarly, the GMU range (0x3d6c000-0x3d9e000) encompasses gpucc (0x3d90000-0x3d99800). These overlaps are typical of Qualcomm SoCs where sub-blocks are carved from larger address regions and managed by different drivers. Not a problem. **Verdict:** Looks correct and well-structured. --- ### Summary The series is in good shape. Two items to address before merging: 1. **Patch 3**: The commit message is stale -- it references adding an `interconnects` property that was actually removed in v3. Needs a reword. 2. **Patch 1**: Minor cosmetic -- extra space before comma in the comment (`On a8xx ,`). Also could benefit from clarifying in the commit message whether this fixes a real regression on existing A8xx hardware or is fixing not-yet-exercised code. --- Generated by Claude Code Patch Reviewer