From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: arm64: dts: qcom: Add GPU support for Kaanapali Date: Sat, 16 May 2026 14:35:13 +1000 Message-ID: In-Reply-To: <20260512-kaana-gpu-dt-v1-5-13e1c07c2050@oss.qualcomm.com> References: <20260512-kaana-gpu-dt-v1-0-13e1c07c2050@oss.qualcomm.com> <20260512-kaana-gpu-dt-v1-5-13e1c07c2050@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Status: Node ordering issue** This is the main patch adding the GPU and GMU nodes. The GPU node at `gpu@3= d00000` and GMU node at `gmu@3d6c000` are both well-structured and follow m= odern Adreno DT conventions. **Node ordering problem:** The patch inserts both `gpu@3d00000` and `gmu@3d= 6c000` before the existing `gxclkctl@3d64000` node: ```diff + gpu: gpu@3d00000 { ... + gmu: gmu@3d6c000 { ... gxclkctl: clock-controller@3d64000 { ``` The correct address-sorted order should be: 1. `gpu@3d00000` 2. `gxclkctl@3d64000` (existing) 3. `gmu@3d6c000` The `gmu` node (0x3d6c000) should be placed **after** `gxclkctl` (0x3d64000= ), not before it. DT convention is to sort sibling nodes by unit address. **GPU node details** - all look correct: - Compatible `"qcom,adreno-44050a01", "qcom,adreno"` matches the binding up= date in patch 2 - Two reg regions (`kgsl_3d0_reg_memory` at 0x6c000 size, `cx_mem` at 0x200= 0 size) =E2=80=94 consistent with the reg layout conditional in the binding - `iommus =3D <&adreno_smmu 0 0x0>, <&adreno_smmu 1 0x0>` =E2=80=94 two IOM= MU contexts with SID 0x0 (newer pattern vs 0x400 on older SoCs) - OPP table ranges from 222MHz to 1.3GHz with proper speed-bin masking (`op= p-supported-hw` narrows from 0x0f to 0x03 at the top bins) - `#cooling-cells =3D <2>` for thermal integration in patch 6 - Interconnect path to `mc_virt SLAVE_EBI1` for memory bandwidth voting **GMU node details:** - Compatible `"qcom,adreno-gmu-840.1", "qcom,adreno-gmu"` =E2=80=94 follows= naming convention - Single reg region ("gmu") only =E2=80=94 older SoCs (sm8450) had three re= gions (gmu, rscc, gmu_pdc). This appears intentional for the A8xx architect= ure but is worth confirming with the author - 5 clocks (ahb, gmu, cxo, memnoc, hub) =E2=80=94 reasonable for this gener= ation - Power domains reference both `GPU_CC_CX_GDSC` and `GX_CLKCTL_GX_GDSC` =E2= =80=94 the GX domain uses the gxclkctl rather than gpucc, which is a newer = pattern seen on recent Qualcomm SoCs - GMU OPP table has 5 frequency points from 475MHz to 750MHz --- --- Generated by Claude Code Patch Reviewer