From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/a8xx: use pipe protect slot 15 for last-span-unbound feature Date: Sat, 16 May 2026 10:05:42 +1000 Message-ID: In-Reply-To: <20260515-adreno-810-v6-5-fbe04c7203e1@pm.me> References: <20260515-adreno-810-v6-0-fbe04c7203e1@pm.me> <20260515-adreno-810-v6-5-fbe04c7203e1@pm.me> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Status: Correct fix, but exposes a pre-existing design issue** The change from `protect->count_max` to hardcoded `15`: ```c - a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(protect->count_max= ), final_cfg); + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg); ``` This is necessary because A810 sets `count_max=3D64` (for its 64 global pro= tect slots), but pipe protect registers only have 16 slots (0-15). The exis= ting X285/A840 coincidentally worked because their `count_max=3D15` happene= d to be the correct pipe slot. **Observation**: After this patch, `count_max` for X285 (15) and A840 (15) = is technically wrong =E2=80=94 they have 52+ global protect entries but `co= unt_max=3D15`, which would fail a `BUILD_BUG_ON(count > count_max)` check i= f one were added. The reason it works is that `__build_asserts()` only chec= ks a660/a690/a730 protect tables, not X285/A840. Consider updating X285 and= A840 to `count_max=3D64` as well for consistency, since the field now only= serves the BUILD_BUG_ON purpose. The fix itself is correct and matches the downstream driver behavior per th= e commit message. --- Generated by Claude Code Patch Reviewer