From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: arm64: dts: renesas: Add Renesas R-Car V4H DSC Date: Sat, 16 May 2026 09:46:53 +1000 Message-ID: In-Reply-To: <20260515-rcar-du-dsc-v2-5-f6b9240a1240@ideasonboard.com> References: <20260515-rcar-du-dsc-v2-0-f6b9240a1240@ideasonboard.com> <20260515-rcar-du-dsc-v2-5-f6b9240a1240@ideasonboard.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Status: Looks good** The DTS changes correctly insert the DSC between DU and DSI1 at the SoC lev= el: ``` DU port@1 (du_out_dsi1) =E2=86=92 DSC port@0 (dsc_in_dsi1) DSC port@1 (dsc_out_dsi1) =E2=86=92 DSI1 port@0 (dsi1_in) ``` The DSC node is `status =3D "disabled"` by default, and the Sparrow Hawk bo= ard enables it: ```c +&dsc { + status =3D "okay"; +}; ``` This is correct because the hardware requires DSC to be enabled for DSI1 to= work. Any board using DSI1 on this SoC must enable the DSC node. The DSC node properties (reg, interrupts, clocks, power-domains, resets) ma= tch both the DT binding (patch 2) and the driver's resource acquisition (pa= tch 3). The clock and reset module IDs (2819) match the clock entry added i= n patch 1. The comment `/* Page 27 / DSI to Display */` on the `&dsc` block matches th= e existing convention in the board file for `&dsi1`. --- **Summary:** The series is well-structured and the approach is appropriate = for enabling bypass-mode DSC. The main actionable item is fixing the error = handling in `rcar_dsc_atomic_enable` to not deassert reset when clock enabl= e fails. Everything else is minor or informational. --- Generated by Claude Code Patch Reviewer