From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/rockchip: analogix_dp: Enable hclk for RK3588 Date: Mon, 25 May 2026 20:40:13 +1000 Message-ID: In-Reply-To: <20260521080835.1362416-6-damon.ding@rock-chips.com> References: <20260521080835.1362416-1-damon.ding@rock-chips.com> <20260521080835.1362416-6-damon.ding@rock-chips.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review ```c + clk =3D devm_clk_get_optional_enabled(dev, "hclk"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "failed to get hclk property\n"); ``` Good use of `devm_clk_get_optional_enabled()` =E2=80=94 the `optional` vari= ant ensures backward compatibility with older DTS that lack the `hclk` entr= y (RK3288, RK3399), while the `enabled` variant keeps the clock on for the = device lifetime via devm. The returned `clk` pointer is intentionally disca= rded since there's no need to toggle it manually. No issues. --- Generated by Claude Code Patch Reviewer