Claude review: clk: renesas: r9a09g047: Add support for SMUX2_DSI{0, 1}_CLK

Claude Code Review Bot
2026-04-12T02:45:56Z

Patch Review

Wires up the PLLDSI SMUX clocks defined in patch 1 to the r9a09g047 SoC definitions. Adds `CPG_SSEL3` register and `SSEL3_SELCTL0`/`SSEL3_SELCTL1`.

No issues.

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