From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: soc: qcom: ubwc: Add configuration Eliza SoC Date: Thu, 05 Mar 2026 13:31:11 +1000 Message-ID: In-Reply-To: <20260304-drm-display-eliza-v2-6-ea0579f62358@oss.qualcomm.com> References: <20260304-drm-display-eliza-v2-0-ea0579f62358@oss.qualcomm.com> <20260304-drm-display-eliza-v2-6-ea0579f62358@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review Adds UBWC v5 configuration for Eliza. Two observations: 1. **TODO comment at line 1956**: `/* TODO: highest_bank_bit =3D 14 for LP_= DDR4 */` =E2=80=94 Is there a plan to handle LP_DDR4 detection, or should t= his be left as-is for now? This is reasonable to leave for initial bringup = but should be tracked. 2. **Table ordering**: The entry is inserted between `kaanapali` and `glymu= r` in the OF table. Alphabetically `eliza` < `glymur` < `kaanapali`, so the= existing table was already not sorted. The new entry is at least placed be= fore `glymur` which is correct relative to that entry. --- Generated by Claude Code Patch Reviewer