From mboxrd@z Thu Jan  1 00:00:00 1970
From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/msm/a6xx: Use barriers while updating HFI Q headers
Date: Wed, 25 Mar 2026 07:32:09 +1000
Message-ID: <review-patch6-20260324-a8xx-gpu-batch2-v1-6-fc95b8d9c017@oss.qualcomm.com>
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Patch Review

Good defensive change. The `dma_mb()` barriers and `READ_ONCE`/`WRITE_ONCE`=
 are appropriate for the shared memory HFI queues between CPU and GMU firmw=
are.

**Nit:** Extra space in comments: `"  Ensure all memory..."` =E2=80=94 two =
spaces after `/*`.

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