From mboxrd@z Thu Jan  1 00:00:00 1970
From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: accel/amdxdna: Add AIE4 power on and off support
Date: Tue, 31 Mar 2026 17:05:10 +1000
Message-ID: <review-patch6-20260330163705.3153647-7-lizhi.hou@amd.com>
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Patch Review

Adds SMU init/fini to the AIE4 firmware load/unload path and NPU3 SMU regis=
ter definitions.

**Issue 1 =E2=80=94 `SMU_ARG_REG` and `SMU_OUT_REG` aliased:**
```c
DEFINE_BAR_OFFSET(SMU_ARG_REG,  NPU3_SMU, MP1_C2PMSG_61_ALT_1),
...
DEFINE_BAR_OFFSET(SMU_OUT_REG,  NPU3_SMU, MP1_C2PMSG_61_ALT_1),
```
Same register for input argument and output. This is the same aliasing patt=
ern as PSP. Appears intentional for the NPU3 hardware protocol.

**Issue 2 =E2=80=94 `SMU_INTR_REG` maps to bar base:**
```c
DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU3_SMU, MMNPU_APERTURE4_BASE),
```
`DEFINE_BAR_OFFSET` computes `(reg_addr) - bar##_BAR_BASE`, and here `NPU3_=
SMU_BAR_BASE =3D MMNPU_APERTURE4_BASE`, so the offset is 0. The interrupt r=
egister is at offset 0 of the SMU BAR. This seems intentional.

**Issue 3 =E2=80=94 No DPM reset before `aie_smu_fini` in AIE4:**
```c
static void aie4_fw_unload(struct amdxdna_dev_hdl *ndev)
{
    aie_psp_stop(ndev->aie.psp_hdl);
    aie_smu_fini(ndev->aie.smu_hdl);
}
```
No DPM level reset before power off. If this is intentional (AIE4 doesn't n=
eed it), it should be documented. If not, it's a bug.

**Overall the series is a reasonable first step.** The main concerns are: t=
he duplicate struct name pattern, the PSP bisection issue between patches 3=
 and 4, the `readx_poll_timeout` pointer arithmetic bug in patch 2, and the=
 UAPI device type gap. The register aliasing patterns should be documented =
for future maintainers.

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