From mboxrd@z Thu Jan  1 00:00:00 1970
From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/panthor: Use a local iomem base for PWR registers
Date: Sun, 12 Apr 2026 09:38:16 +1000
Message-ID: <review-patch6-20260410164637.549145-7-karunika.choo@arm.com>
In-Reply-To: <20260410164637.549145-7-karunika.choo@arm.com>
References: <20260410164637.549145-1-karunika.choo@arm.com> <20260410164637.549145-7-karunika.choo@arm.com>
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Patch Review

**Critical issue:**

**Regression bug in `panthor_hw.c`**: This patch changes the PWR register offsets from absolute to relative. For example:
```c
// Before (absolute):
#define PWR_L2_PRESENT   PWR_CTRL_REG(0x100)   // = 0x900
// After (relative):
#define PWR_L2_PRESENT   0x100
```

But `panthor_hw.c` (in `panthor_gpu_info_init`) still reads these registers using `ptdev->iomem`:
```c
ptdev->gpu_info.l2_present = gpu_read64(ptdev->iomem, PWR_L2_PRESENT);
ptdev->gpu_info.tiler_present = gpu_read64(ptdev->iomem, PWR_TILER_PRESENT);
ptdev->gpu_info.shader_present = gpu_read64(ptdev->iomem, PWR_SHADER_PRESENT);
```

After this patch, `PWR_L2_PRESENT` is `0x100` instead of `0x900`, so this code reads GPU_SHADER_PRESENT (offset 0x100) instead of PWR_L2_PRESENT (offset 0x900). Similarly, `PWR_TILER_PRESENT` (now `0x140`) would read SHADER_READY (offset 0x140), and `PWR_SHADER_PRESENT` (now `0x200`) would read SHADER_PWRTRANS (offset 0x200). **This is silent data corruption of the gpu_info fields on arch 14.x hardware.**

This must be fixed, either by:
- Adding PWR present-register read helpers in patch 3 (preferred, consistent with the series' approach)
- Updating `panthor_hw.c` in this patch to use `ptdev->pwr->iomem`

Additionally, in the IRQ base change:
```c
err = panthor_request_pwr_irq(ptdev, &pwr->irq, irq,
                              PWR_INTERRUPTS_MASK,
-                             GPU_CONTROL_BASE + PWR_CONTROL_BASE);
+                             GPU_CONTROL_BASE + PWR_INT_BASE);
```
Since `PWR_INT_BASE` is `0x800` (same as `PWR_CONTROL_BASE`), this is a no-op change in practice, but it makes the intent clearer -- the IRQ registers happen to start at the base of the PWR control block.

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