From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/panthor: Use a local iomem base for PWR registers Date: Mon, 13 Apr 2026 19:05:53 +1000 Message-ID: In-Reply-To: <20260412142951.2309135-7-karunika.choo@arm.com> References: <20260412142951.2309135-1-karunika.choo@arm.com> <20260412142951.2309135-7-karunika.choo@arm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Status: Good, with one pre-existing bug noted.** Adds `void __iomem *iomem` to `struct panthor_pwr`, set to `ptdev->iomem + = GPU_CONTROL_BASE + PWR_CONTROL_BASE`: ```c + pwr->iomem =3D ptdev->iomem + GPU_CONTROL_BASE + PWR_CONTROL_BASE; ``` Since `GPU_CONTROL_BASE` is 0x0, this effectively becomes `ptdev->iomem + 0= x800`, which is correct for the power management register block. Register defines are rebased =E2=80=94 for example, `TILER_PWRTRANS` change= s from a `PWR_CTRL_REG()` macro invocation to a plain offset relative to PW= R_CONTROL_BASE: ```c -#define TILER_PWRTRANS PWR_CTRL_REG(0x18) +#define TILER_PWRTRANS 0x18 ``` The IRQ iomem for PWR is set to `ptdev->iomem + PWR_INT_BASE` where `PWR_IN= T_BASE` becomes 0x800 (same as `PWR_CONTROL_BASE`). Looking at the Mali reg= ister map, the PWR interrupt registers are indeed at offset 0x800 from the = GPU base =E2=80=94 this is because the PWR_INT registers happen to be at th= e start of the PWR block. Correct. **Pre-existing bug (not introduced by this series):** In `panthor_pwr_l2_po= wer_on()`: ```c const u32 pwr_status =3D gpu_read64(pwr->iomem, L2_PWRTRANS); ``` `gpu_read64` returns `u64`, but the result is stored in a `u32`. This silen= tly truncates the upper 32 bits. For current hardware with =E2=89=A432 shad= er cores this is harmless, but it's technically wrong. This truncation exis= ts in the current code as well =E2=80=94 the patch merely changes the iomem= argument, not the type. Worth fixing separately. --- --- Generated by Claude Code Patch Reviewer