From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm: Add a6xx+ perfcntr tables Date: Thu, 23 Apr 2026 09:13:14 +1000 Message-ID: In-Reply-To: <20260420222621.417276-7-robin.clark@oss.qualcomm.com> References: <20260420222621.417276-1-robin.clark@oss.qualcomm.com> <20260420222621.417276-7-robin.clark@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Introduces `msm_perfcntr.h` with the `msm_perfcntr_counter` and `msm_perfcntr_group` structs, and wires up the generated perfcntr tables in `a6xx_gpu_init()`. Minor nit: The `GROUP` macro and `fd_perfcntr_counter`/`fd_perfcntr_group` aliases at the bottom of the header are inherited from mesa's naming convention. The aliases let the generated code use mesa names -- this is fine, just worth noting for future readers. The family range checks in `a6xx_gpu_init()` could become stale as new GPU families are added: ```c } else if ((ADRENO_8XX_GEN1 <= config->info->family) && (config->info->family <= ADRENO_8XX_GEN2)) { ``` Consider using a `>=` for the upper bound or a fallthrough, so new 8xx gens don't silently get no perfcntr support. --- Generated by Claude Code Patch Reviewer