From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/adreno: add Adreno 810 GPU support Date: Sat, 16 May 2026 10:05:42 +1000 Message-ID: In-Reply-To: <20260515-adreno-810-v6-6-fbe04c7203e1@pm.me> References: <20260515-adreno-810-v6-0-fbe04c7203e1@pm.me> <20260515-adreno-810-v6-6-fbe04c7203e1@pm.me> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Status: Mostly good, minor issues** This is the main enablement patch adding the catalog entry, register lists,= and helper function. **Catalog entry** (`adreno_info` for chip_id `0x44010000`): - Family `ADRENO_8XX_GEN1` =E2=80=94 correct, this is the first GEN1 device - Firmware `gen80300_*` =E2=80=94 distinct from X285 (gen80100) and A840 (g= en80200), no AQE firmware - GMEM `SZ_512K + SZ_64K` =3D 576K =E2=80=94 significantly smaller than X28= 5 (21MB) and A840 (18MB), consistent with a mid-range part - Quirks include `ADRENO_QUIRK_IFPC` but not `ADRENO_QUIRK_SOFTFUSE` =E2=80= =94 correct, uses regular efuse per the DTS - Reuses `a840_gbif` for `.gbif_cx` =E2=80=94 seems intentional - `max_slices =3D 1` =E2=80=94 simpler than X285 (4) and A840 (3) - `gmu_chipid =3D 0x8030000` =E2=80=94 the zero minor/revision fields are n= oted - `preempt_record_size =3D 4558 * SZ_1K` =E2=80=94 specific to this GPU **Unused helper**: `adreno_is_a810()` is defined but never called in this s= eries. While `adreno_is_a840()` and `adreno_is_x285()` have existing caller= s, adding an unused function is unnecessary =E2=80=94 it can be added when = actually needed. **RSCC question**: The existing code at `a6xx_gmu.c:648` uses `adreno_is_a8= 40()` to select `BIT(30)` vs `BIT(16)` for RSCC status polling. Does A810 n= eed the `BIT(30)` path? This may be handled by the dependent RSCC offset fi= x series, but worth confirming. **Register lists** look thorough: - `a810_nonctxt_regs`: Well-commented entries for ECO controls and chicken = bits - `a810_protect_regs`: 47 entries with `DECLARE_ADRENO_PROTECT(a810_protect= , 64)` =E2=80=94 correctly sized - `a810_ifpc_reglist_regs`: Includes all 64 `CP_PROTECT_GLOBAL` entries (0-= 63) for IFPC preservation - `a810_dyn_pwrup_reglist_regs`: Includes the hardcoded `CP_PROTECT_PIPE(15= )` matching the fix in patch 5 --- Generated by Claude Code Patch Reviewer