From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: Re: [PATCH 6/6] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB3 SuperSpeed Date: Mon, 25 May 2026 19:16:37 +1000 Message-ID: In-Reply-To: <340451f1-f397-4eb9-b6ff-8c6ae1bcefcb@linaro.org> References: <20260522060645.4399-1-graham.oconnor@gmail.com> <340451f1-f397-4eb9-b6ff-8c6ae1bcefcb@linaro.org> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review ```dts +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p912>; + /delete-property/ orientation-switch; + status = "okay"; ``` **Generally looks correct.** The use of `/delete-property/ orientation-switch` is appropriate since this is a fixed USB-A connector (no orientation detection needed). The lane assignment with DP on lanes 0-1 and USB3 SS on lanes 2-3 follows the standard QMP combo PHY split. ```dts + usb3_con: connector { + compatible = "usb-a-connector"; ``` The USB-A connector node with dual-port (HS + SS) configuration is properly structured. **Minor**: The `&usb_1` node sets `dr_mode = "host"` but doesn't set `status = "okay"` for the DWC3 child. If the base DTS has the DWC3 disabled, USB won't work. However, this depends on the base DTS defaults which may already have it enabled. **Minor**: The `&usb_1_dwc3_hs` endpoint override is placed between the connector block and the `&usb_1` block, which works but reads slightly disjointed. --- Generated by Claude Code Patch Reviewer