Claude review: drm/msm/dpu: Add support for Eliza SoC

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

This is the main catalog patch (DPU v12.4). One issue:

**Bug: `eliza_cwb` defined but not used.** At lines 2531-2532:
```c
.cwb_count = ARRAY_SIZE(eliza_cwb),
.cwb = sm8650_cwb,
```

The patch defines `eliza_cwb[]` with `.len = 0x20` for each entry (lines 2419-2436), but the `dpu_eliza_cfg` struct references `sm8650_cwb` which has `.len = 0x8`. This makes `eliza_cwb` dead code. The correct CWB len for Eliza is likely `0x20` (matching `sm8750_cwb` which also has `0x20`), so this should be:
```c
.cwb = eliza_cwb,
```

Note: this mirrors a pre-existing bug in `dpu_12_0_sm8750.h:485-486` where `sm8750_cwb` is defined with `.len = 0x20` but `.cwb = sm8650_cwb` is used. That should also be fixed separately.

Other observations on this patch:
- **TODO at line 2495**: `/* TODO: macrotile-qseed is different from macrotile */` in `eliza_perf_data.qos_lut_tbl` — the QoS LUT table reuses `sc7180_qos_*` entries. This may need tuning for production but is reasonable for initial bringup.
- The `sm8650_vbif` reuse (line 2535-2536) follows the same pattern as SM8750 and Glymur.
- DSC has only 3 entries (DSC_0, DSC_1, DSC_2) vs 4 on SM8750, consistent with fewer blocks on Eliza.
- LM_3 at line 2298 intentionally has no `.dspp` assignment (only 3 DSPPs for 4 LMs), which is a valid configuration.

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