From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/dpu: Add support for Eliza SoC Date: Thu, 05 Mar 2026 13:31:11 +1000 Message-ID: In-Reply-To: <20260304-drm-display-eliza-v2-7-ea0579f62358@oss.qualcomm.com> References: <20260304-drm-display-eliza-v2-0-ea0579f62358@oss.qualcomm.com> <20260304-drm-display-eliza-v2-7-ea0579f62358@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review This is the main catalog patch (DPU v12.4). One issue: **Bug: `eliza_cwb` defined but not used.** At lines 2531-2532: ```c .cwb_count =3D ARRAY_SIZE(eliza_cwb), .cwb =3D sm8650_cwb, ``` The patch defines `eliza_cwb[]` with `.len =3D 0x20` for each entry (lines = 2419-2436), but the `dpu_eliza_cfg` struct references `sm8650_cwb` which ha= s `.len =3D 0x8`. This makes `eliza_cwb` dead code. The correct CWB len for= Eliza is likely `0x20` (matching `sm8750_cwb` which also has `0x20`), so t= his should be: ```c .cwb =3D eliza_cwb, ``` Note: this mirrors a pre-existing bug in `dpu_12_0_sm8750.h:485-486` where = `sm8750_cwb` is defined with `.len =3D 0x20` but `.cwb =3D sm8650_cwb` is u= sed. That should also be fixed separately. Other observations on this patch: - **TODO at line 2495**: `/* TODO: macrotile-qseed is different from macrot= ile */` in `eliza_perf_data.qos_lut_tbl` =E2=80=94 the QoS LUT table reuses= `sc7180_qos_*` entries. This may need tuning for production but is reasona= ble for initial bringup. - The `sm8650_vbif` reuse (line 2535-2536) follows the same pattern as SM87= 50 and Glymur. - DSC has only 3 entries (DSC_0, DSC_1, DSC_2) vs 4 on SM8750, consistent w= ith fewer blocks on Eliza. - LM_3 at line 2298 intentionally has no `.dspp` assignment (only 3 DSPPs f= or 4 LMs), which is a valid configuration. --- Generated by Claude Code Patch Reviewer