From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: docs: gpu: nova-core: Document the PRAMIN aperture mechanism Date: Wed, 01 Apr 2026 07:33:01 +1000 Message-ID: In-Reply-To: <20260311004008.2208806-8-joelagnelf@nvidia.com> References: <20260311004008.2208806-1-joelagnelf@nvidia.com> <20260311004008.2208806-8-joelagnelf@nvidia.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review The TLB flush implementation looks correct. The `read_poll_timeout` with a 2-second timeout matching Nouveau is appropriate. **Observation:** The TLB register addresses (`0x00b830a0`, `0x00b830a4`, `0x00b830b0`) -- these are MMU_PRI addresses. Worth confirming they're correct for the target GPU families (Ampere/Turing). **Minor:** The lock comment about DMA fence signalling is good but duplicated verbatim from the PRAMIN module. Consider factoring this into a shared doc reference. --- Generated by Claude Code Patch Reviewer