From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: arm64: dts: qcom: milos: Add Adreno 810 GPU and GMU nodes Date: Tue, 05 May 2026 08:55:17 +1000 Message-ID: In-Reply-To: <20260502-adreno-810-v5-7-bc9fd2bb788d@pm.me> References: <20260502-adreno-810-v5-0-bc9fd2bb788d@pm.me> <20260502-adreno-810-v5-7-bc9fd2bb788d@pm.me> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Status: Looks good** Adds complete GPU and GMU device tree nodes for the Milos SoC. Key points: **GPU node:** - Compatible: `"qcom,adreno-44010000", "qcom,adreno"` =E2=80=94 matches bin= ding from patch 2 - Three register regions: `kgsl_3d0_reg_memory`, `cx_mem`, `cx_dbgc` - Uses nvmem cell for speedbin (`gpu_speed_bin`) - Single interconnect path (`gfx-mem`) - OPP table with 10 frequency points from 264MHz to 1150MHz, with `opp-supp= orted-hw` masks for speedbinning (the 1150MHz entry only supports bins 0 an= d 1 with mask `0x3`) - The `qcom,opp-acd-level` properties provide ACD (Adaptive Clock Distribut= ion) tuning values **GMU node:** - Compatible: `"qcom,adreno-gmu-810.0", "qcom,adreno-gmu"` =E2=80=94 matche= s binding from patch 1 - Single register region (`gmu`) =E2=80=94 consistent with the binding lack= ing RSCC - 6 clocks matching the binding specification - Two power domains: CX and GX (using the kaanapali-gxclkctl.h header as ex= plained in commit message) - GMU OPP table with 2 entries (350MHz and 650MHz) **Header reuse**: The commit message explains why `qcom,kaanapali-gxclkctl.= h` is used instead of a milos-specific header =E2=80=94 same driver, same `= GX_CLKCTL_GX_GDSC` definition. Has `Reviewed-by: Dmitry Baryshkov`. The node is placed before `gxclkctl` which is the correct ordering since th= e GPU references `gxclkctl` via power-domains. No issues found. --- Generated by Claude Code Patch Reviewer