From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/bridge: tc358762: Update comment about the number of lanes Date: Sat, 16 May 2026 12:04:23 +1000 Message-ID: In-Reply-To: <20260513-tc358762-fixes-v3-7-6698b55008b9@ideasonboard.com> References: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> <20260513-tc358762-fixes-v3-7-6698b55008b9@ideasonboard.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Replaces the `TODO: Find out how to get dual-lane mode working` with a clear explanation of *why* only 1 lane works: with DSI clock as pixel clock source, the divider is `bitspp / 8 / nlanes`. For RGB888, nlanes=1 gives divider=3, nlanes=2 would need divider=1.5 which isn't possible. This is a good explanation that saves future developers from going down a rabbit hole. The comment references `SYSCTRL_PCLKDIV_DIV_2` and `SYSCTRL_PCLKDIV_DIV_3` defined in patch 2, making the connection clear. No issues. **Reviewed-by worthy.** --- Generated by Claude Code Patch Reviewer