From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: clk: renesas: r9a09g047: Add support for DSI clocks and resets Date: Sun, 12 Apr 2026 12:45:57 +1000 Message-ID: In-Reply-To: <21ac6da825e8fad0b0a9d37d6daa955b0d23ce07.1775636898.git.tommaso.merciai.xr@bp.renesas.com> References: <21ac6da825e8fad0b0a9d37d6daa955b0d23ce07.1775636898.git.tommaso.merciai.xr@bp.renesas.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review **Observation**: `dsi_0_vclk1` uses `CLK_SMUX2_DSI0_CLK` and `dsi_0_vclk2` uses `CLK_SMUX2_DSI1_CLK`. This means vclk1 is sourced from PLLDSI0's mux and vclk2 from PLLDSI1's mux, which aligns with the cover letter description. **Minor note**: The `dsi_0_vclk2` entry is placed after `tsu_1_pclk` at a distant location (module index 25,0 vs 14,x for the other DSI clocks). This matches the hardware register layout but could use a comment explaining why it's separate from the other DSI module clocks. However this may just be the natural ordering. No issues. --- Generated by Claude Code Patch Reviewer