Claude review: dt-bindings: display: bridge: renesas, dsi: Add support for RZ/G3E SoC

Claude Code Review Bot
2026-04-12T02:45:58Z

Patch Review

Major restructuring of the DSI bridge bindings. This moves from inline clock descriptions to per-SoC conditional blocks.

**Issue 1 (binding correctness)**: The `data-lanes` required constraint was previously at the top level under port@1 for all SoCs. Now it's been moved into per-SoC conditional blocks. The `else` branch handles non-RZ/G3E SoCs:

```yaml
else:
properties:
ports:
properties:
port@1:
properties:
endpoint:
properties:
data-lanes: true
required:
- data-lanes
```

This looks correct for maintaining backward compatibility.

**Issue 2**: For RZ/G3E, the binding defines three ports (`port@0`, `port@1`, `port@2`) with `port@2` being the output port with `data-lanes`. However, `port@1` explicitly says `data-lanes: false`. This makes sense — port@0 and port@1 are inputs from DU0 and DU1 respectively, port@2 is the DSI output.

**Note**: The clock-names for RZ/G3E include `vclk2` as a 6th clock, which is consistent with the driver changes in patches 13-14.

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