Claude review: gpu: nova-core: mm: Add common memory management types

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

Well-structured bitfield types for `VramAddress`, `VirtualAddress`, `Pfn`, `Vfn`.

Concern with `VirtualAddress::level_index()`:
```rust
// L5 is only used by MMU v3 (PTE level).
5 => self.l4_index(),
_ => 0,
```
L5 returns `l4_index()` -- this seems like it could be a bug. If v3 has a 6-level hierarchy, L5 should have its own index bits. Looking at the `VirtualAddress` bitfield, there is no `l5_index` field defined. This means the v3 PTE level reuses L4's index bits. This may be intentional if v3 PTE pages have the same index extraction as v2's L4, but it deserves a more detailed comment explaining the rationale. The `_ => 0` catch-all silently returns 0 for any unexpected level, which could mask bugs.

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