From mboxrd@z Thu Jan  1 00:00:00 1970
From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/tyr: add MMU module
Date: Tue, 03 Mar 2026 12:48:19 +1000
Message-ID: <review-patch8-20260302232500.244489-9-deborah.brouwer@collabora.com>
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Patch Review

**Author:** Boris Brezillon

The MMU module wraps the slot manager for address space management.

In `Mmu::new()`:

```rust
+        let slot_count =3D gpu_info.as_present.count_ones().try_into()?;
```

`count_ones()` returns `u32`, and `try_into()` converts to `usize`. This ca=
n't fail in practice on any supported platform, but the `?` is harmless.

In `driver.rs`, the MMU is created but the result is initially unused:

```rust
+        let _mmu =3D Mmu::new(pdev, iomem.as_arc_borrow(), &gpu_info)?;
```

This is later replaced in patch 12 with `let mmu =3D ...` when firmware loa=
ding is added. This is fine for the incremental build-up approach.

The `AddressSpaceManager`'s `dev()` method has a safety comment:

```rust
+    fn dev(&self) -> &Device<Bound> {
+        // SAFETY: pdev is a bound device.
+        unsafe { self.pdev.as_ref().as_bound() }
+    }
```

This is called from `evict()` which can happen during driver teardown. If t=
he device has been unbound by the time eviction happens, this would be unso=
und. However, the `iomem.try_access().is_some()` check in `evict()` should =
gate this =E2=80=94 if devres has been released, `try_access()` returns `No=
ne` and the device operations are skipped. This appears safe.

The `mair_to_memattr()` function translates AArch64 MAIR register values to=
 GPU memory attributes. The logic matches the C panthor driver's `panthor_m=
mu_as_enable()`. The comment about non-coherent systems (`TODO: this assume=
s a non-coherent system`) is good to keep visible.

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