[PATCH v4 38/39] drm/msm/dpu: use msm_dp_get_mst_intf_id() to get the intf id

Yongxing Mou
2026-04-10T09:37:06Z

From: Abhinav Kumar <quic_abhinavk@quicinc.com>

Use msm_dp_get_mst_intf_id() to get the interface ID for the DP MST
controller as the intf_id is unique for each MST stream of each DP
controller.

For DSI/eDP/DP SST, the stream_id is always 0, so existing behavior
remains unchanged.

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20 +++++++++++---------
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 ++++
3 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index eba1d52211f6..d6813107a27d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1438,18 +1438,21 @@ static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc,

static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog,
struct dpu_rm *dpu_rm,
- enum dpu_intf_type type, u32 controller_id)
+ struct msm_display_info *disp_info, u32 controller_id)
{
- int i = 0;
+ int i = 0, cnt = 0;
+ int stream_id = disp_info->stream_id;

- if (type == INTF_WB)
+ if (disp_info->intf_type == INTF_WB)
return NULL;

+ DPU_DEBUG("intf_type 0x%x controller_id %d stream_id %d\n",
+ disp_info->intf_type, controller_id, stream_id);
for (i = 0; i < catalog->intf_count; i++) {
- if (catalog->intf[i].type == type
- && catalog->intf[i].controller_id == controller_id) {
- return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id);
- }
+ if (catalog->intf[i].type == disp_info->intf_type &&
+ controller_id == catalog->intf[i].controller_id)
+ if (cnt++ == stream_id)
+ return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id);
}

return NULL;
@@ -2675,8 +2678,7 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
i, controller_id, phys_params.split_role);

phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm,
- disp_info->intf_type,
- controller_id);
+ disp_info, controller_id);

if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX)
phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index ca1ca2e51d7e..2eb4c39b111c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -28,6 +28,7 @@
* @h_tile_instance: Controller instance used per tile. Number of elements is
* based on num_of_h_tiles
* @is_cmd_mode Boolean to indicate if the CMD mode is requested
+ * @stream_id stream id for which the interface needs to be acquired
* @vsync_source: Source of the TE signal for DSI CMD devices
*/
struct msm_display_info {
@@ -35,6 +36,7 @@ struct msm_display_info {
uint32_t num_of_h_tiles;
uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
bool is_cmd_mode;
+ int stream_id;
enum dpu_vsync_source vsync_source;
};

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 89868443c0fe..305d4c76098d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -612,6 +612,7 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
info.h_tile_instance[info.num_of_h_tiles++] = other;

info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->kms->dsi[i]);
+ info.stream_id = 0;

rc = dpu_kms_dsi_set_te_source(&info, priv->kms->dsi[i]);
if (rc) {
@@ -687,6 +688,7 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev,
}

for (stream_id = 0; stream_id < stream_cnt; stream_id++) {
+ info.stream_id = stream_id;
encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DPMST, &info);
if (IS_ERR(encoder)) {
DPU_ERROR("encoder init failed for dp mst display\n");
@@ -720,6 +722,7 @@ static int _dpu_kms_initialize_hdmi(struct drm_device *dev,
info.num_of_h_tiles = 1;
info.h_tile_instance[0] = 0;
info.intf_type = INTF_HDMI;
+ info.stream_id = 0;

encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS, &info);
if (IS_ERR(encoder)) {
@@ -752,6 +755,7 @@ static int _dpu_kms_initialize_writeback(struct drm_device *dev,
/* use only WB idx 2 instance for DPU */
info.h_tile_instance[0] = wb_idx;
info.intf_type = INTF_WB;
+ info.stream_id = 0;

maxlinewidth = dpu_rm_get_wb(&dpu_kms->rm, info.h_tile_instance[0])->caps->maxlinewidth;

--
2.43.0