[PATCH v4 16/39] drm/msm/dp: use stream_id to change offsets in dp_catalog

Yongxing Mou
2026-04-10T09:35:18Z

From: Abhinav Kumar <quic_abhinavk@quicinc.com>

Use the dp_panel's stream_id to adjust the offsets for stream 1 which will
be used for MST in the dp_catalog. Stream 1 share the same link clk with
stream 0 with different reg offset. Also add additional register defines
for stream 1.

Streams 2 and 3 are not covered here, as they use separate link clocks and
require separate handling.

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
---
drivers/gpu/drm/msm/dp/dp_ctrl.c | 24 ++++++++++---
drivers/gpu/drm/msm/dp/dp_panel.c | 72 +++++++++++++++++++++++++++------------
drivers/gpu/drm/msm/dp/dp_reg.h | 11 ++++++
3 files changed, 81 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 1e80d6fc7bda..a52bcd9ea2a3 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -393,6 +393,7 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl,
struct msm_dp_panel *msm_dp_panel)
{
u32 config = 0, tbd;
+ u32 reg_offset = 0;

config = msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL);

@@ -409,7 +410,8 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl,

drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=0x%x\n", config);

- msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config);
+ if (msm_dp_panel->stream_id == DP_STREAM_1)
+ reg_offset = REG_DP1_CONFIGURATION_CTRL - REG_DP_CONFIGURATION_CTRL;
}

static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl)
@@ -460,12 +462,16 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl,
struct msm_dp_panel *msm_dp_panel)
{
u32 colorimetry_cfg, test_bits_depth, misc_val;
+ u32 reg_offset = 0;

test_bits_depth = msm_dp_link_get_test_bits_depth(ctrl->link,
msm_dp_panel->msm_dp_mode.bpp);
colorimetry_cfg = msm_dp_link_get_colorimetry_config(ctrl->link);

- misc_val = msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0);
+ if (msm_dp_panel->stream_id == DP_STREAM_1)
+ reg_offset = REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0;
+
+ misc_val = msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset);

/* clear bpp bits */
misc_val &= ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT);
@@ -475,7 +481,7 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl,
misc_val |= DP_MISC0_SYNCHRONOUS_CLK;

drm_dbg_dp(ctrl->drm_dev, "misc settings = 0x%x\n", misc_val);
- msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val);
+ msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset, misc_val);
}

static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl,
@@ -2446,6 +2452,7 @@ static int msm_dp_ctrl_link_retrain(struct msm_dp_ctrl_private *ctrl)
}

static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl,
+ struct msm_dp_panel *msm_dp_panel,
u32 rate, u32 stream_rate_khz,
bool is_ycbcr_420)
{
@@ -2455,6 +2462,12 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl,
u32 const link_rate_hbr2 = 540000;
u32 const link_rate_hbr3 = 810000;
unsigned long den, num;
+ u32 mvid_reg_off = 0, nvid_reg_off = 0;
+
+ if (msm_dp_panel->stream_id == DP_STREAM_1) {
+ mvid_reg_off = REG_DP1_SOFTWARE_MVID - REG_DP_SOFTWARE_MVID;
+ nvid_reg_off = REG_DP1_SOFTWARE_NVID - REG_DP_SOFTWARE_NVID;
+ }

switch (rate) {
case link_rate_hbr3:
@@ -2509,8 +2522,8 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl,
nvid *= 3;

drm_dbg_dp(ctrl->drm_dev, "mvid=0x%x, nvid=0x%x\n", mvid, nvid);
- msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID, mvid);
- msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid);
+ msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID + mvid_reg_off, mvid);
+ msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID + nvid_reg_off, nvid);
}

int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train)
@@ -2585,6 +2598,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *
msm_dp_ctrl_configure_source_params(ctrl, msm_dp_panel);

msm_dp_ctrl_config_msa(ctrl,
+ msm_dp_panel,
ctrl->link->link_params.rate,
pixel_rate_orig,
msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420);
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c
index c17b87353d1a..6c88cc7e3037 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.c
+++ b/drivers/gpu/drm/msm/dp/dp_panel.c
@@ -447,27 +447,35 @@ static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, struct
u32 header[2];
u32 val;
int i;
+ u32 offset = 0;
+
+ if (panel->msm_dp_panel.stream_id == DP_STREAM_1)
+ offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;

msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header);

- msm_dp_write_link(panel, MMSS_DP_GENERIC0_0, header[0]);
- msm_dp_write_link(panel, MMSS_DP_GENERIC0_1, header[1]);
+ msm_dp_write_link(panel, MMSS_DP_GENERIC0_0 + offset, header[0]);
+ msm_dp_write_link(panel, MMSS_DP_GENERIC0_1 + offset, header[1]);

for (i = 0; i < sizeof(vsc_sdp->db); i += 4) {
val = ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i + 2] << 16) |
(vsc_sdp->db[i + 3] << 24));
- msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i, val);
+ msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i + offset, val);
}
}

static void msm_dp_panel_update_sdp(struct msm_dp_panel_private *panel)
{
u32 hw_revision = panel->msm_dp_panel.hw_revision;
+ u32 offset = 0;
+
+ if (panel->msm_dp_panel.stream_id == DP_STREAM_1)
+ offset = MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3;

if (hw_revision >= DP_HW_VERSION_1_0 &&
hw_revision < DP_HW_VERSION_1_2) {
- msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, UPDATE_SDP);
- msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, 0x0);
+ msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, UPDATE_SDP);
+ msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, 0x0);
}
}

@@ -476,16 +484,25 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sd
struct msm_dp_panel_private *panel =
container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);
u32 cfg, cfg2, misc;
+ u32 misc_reg_offset = 0;
+ u32 sdp_cfg_offset = 0;
+ u32 sdp_cfg2_offset = 0;
+
+ if (msm_dp_panel->stream_id == DP_STREAM_1) {
+ misc_reg_offset = REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0;
+ sdp_cfg_offset = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
+ sdp_cfg2_offset = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
+ }

- cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG);
- cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2);
- misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0);
+ cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset);
+ cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset);
+ misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset);

cfg |= GEN0_SDP_EN;
- msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg);
+ msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg);

cfg2 |= GENERIC0_SDPSIZE_VALID;
- msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2);
+ msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2);

msm_dp_panel_send_vsc_sdp(panel, vsc_sdp);

@@ -495,7 +512,7 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sd
drm_dbg_dp(panel->drm_dev, "vsc sdp enable=1\n");

pr_debug("misc settings = 0x%x\n", misc);
- msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc);
+ msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc);

msm_dp_panel_update_sdp(panel);
}
@@ -505,16 +522,25 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel)
struct msm_dp_panel_private *panel =
container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);
u32 cfg, cfg2, misc;
+ u32 misc_reg_offset = 0;
+ u32 sdp_cfg_offset = 0;
+ u32 sdp_cfg2_offset = 0;
+
+ if (msm_dp_panel->stream_id == DP_STREAM_1) {
+ misc_reg_offset = REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0;
+ sdp_cfg_offset = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
+ sdp_cfg2_offset = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
+ }

- cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG);
- cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2);
- misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0);
+ cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset);
+ cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset);
+ misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset);

cfg &= ~GEN0_SDP_EN;
- msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg);
+ msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg);

cfg2 &= ~GENERIC0_SDPSIZE_VALID;
- msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2);
+ msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2);

/* switch back to MSA */
misc &= ~DP_MISC1_VSC_SDP;
@@ -522,7 +548,7 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel)
drm_dbg_dp(panel->drm_dev, "vsc sdp enable=0\n");

pr_debug("misc settings = 0x%x\n", misc);
- msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc);
+ msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc);

msm_dp_panel_update_sdp(panel);
}
@@ -580,6 +606,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en)
u32 msm_dp_active;
u32 total;
u32 reg;
+ u32 offset = 0;

panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);
drm_mode = &panel->msm_dp_panel.msm_dp_mode.drm_mode;
@@ -594,6 +621,9 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en)
drm_mode->vsync_start - drm_mode->vdisplay,
drm_mode->vsync_end - drm_mode->vsync_start);

+ if (msm_dp_panel->stream_id == DP_STREAM_1)
+ offset = REG_DP1_TOTAL_HOR_VER - REG_DP_TOTAL_HOR_VER;
+
total_hor = drm_mode->htotal;

total_ver = drm_mode->vtotal;
@@ -624,10 +654,10 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en)

msm_dp_active = data;

- msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER, total);
- msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC, sync_start);
- msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blanking);
- msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER, msm_dp_active);
+ msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER + offset, total);
+ msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC + offset, sync_start);
+ msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, width_blanking);
+ msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER + offset, msm_dp_active);

reg = msm_dp_read_pn(panel, MMSS_DP_INTF_CONFIG);
if (wide_bus_en)
diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h
index 3689642b7fc0..295c1161e6b7 100644
--- a/drivers/gpu/drm/msm/dp/dp_reg.h
+++ b/drivers/gpu/drm/msm/dp/dp_reg.h
@@ -332,6 +332,17 @@
#define DP_TPG_VIDEO_CONFIG_BPP_8BIT (0x00000001)
#define DP_TPG_VIDEO_CONFIG_RGB (0x00000004)

+/* DP MST registers */
+#define REG_DP1_CONFIGURATION_CTRL (0x00000400)
+#define REG_DP1_SOFTWARE_MVID (0x00000414)
+#define REG_DP1_SOFTWARE_NVID (0x00000418)
+#define REG_DP1_TOTAL_HOR_VER (0x0000041C)
+#define REG_DP1_MISC1_MISC0 (0x0000042C)
+#define MMSS_DP1_GENERIC0_0 (0x00000490)
+#define MMSS_DP1_SDP_CFG (0x000004E0)
+#define MMSS_DP1_SDP_CFG2 (0x000004E4)
+#define MMSS_DP1_SDP_CFG3 (0x000004E8)
+
#define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088)

#define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C)

--
2.43.0