From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/bridge: tc358762: Support VTG Date: Sat, 16 May 2026 12:04:23 +1000 Message-ID: In-Reply-To: <20260513-tc358762-fixes-v3-8-6698b55008b9@ideasonboard.com> References: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> <20260513-tc358762-fixes-v3-8-6698b55008b9@ideasonboard.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review Adds Video Timing Generator support. When VTG is enabled, the TC358762 gene= rates DPI output timings from its internal registers rather than duplicatin= g DSI input timings. This fixes observed hsync instability. The implementation: - Adds VTG register defines (`LCDC_HSR_HBPR`, `LCDC_HDISPR_HFPR`, etc.) - Converts `drm_display_mode` to `videomode` and programs the timing regist= ers - Sets `LCDCTRL_VTGEN` and triggers `LCDC_VFUEN` to upload timings - Adds `use_vtg` flag, hardcoded to `true` in probe The `use_vtg` field and conditional could be simplified to always-on code s= ince it's hardcoded to `true`, but keeping it as a flag makes the code self= -documenting and leaves room for future configurability. This is reasonable. One observation: `struct videomode vm =3D { 0 }` =E2=80=94 the preferred ke= rnel style is `=3D { }` or `=3D {}`, but `=3D { 0 }` works fine and is comm= on enough. No issues. **Reviewed-by worthy.** --- Generated by Claude Code Patch Reviewer