From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: clk: renesas: r9a09g047: Add support for LCDC{0, 1} clocks and resets Date: Sun, 12 Apr 2026 12:45:57 +1000 Message-ID: In-Reply-To: References: X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Adds LCDC0 and LCDC1 module clocks (aclk, pclk, dclk) and reset entries. LCDC0's dclk uses `CLK_SMUX2_DSI0_CLK` and LCDC1's dclk uses `CLK_SMUX2_DSI1_CLK`, consistent with patch 7. **Minor alignment nit**: Some `DEF_MOD` entries use different indentation for the `BUS_MSTOP` continuation line compared to the surrounding entries (single tab vs double tab). This might be from merging with code that has slightly different formatting. Not a blocking issue. No issues. --- Generated by Claude Code Patch Reviewer