From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: staging: media: tegra-video: tegra20: add support for second output of VI Date: Wed, 04 Mar 2026 07:48:07 +1000 Message-ID: In-Reply-To: <20260303084239.15007-10-clamor95@gmail.com> References: <20260303084239.15007-1-clamor95@gmail.com> <20260303084239.15007-10-clamor95@gmail.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Converts first-output-specific register defines to parameterized macros like `TEGRA_VI_VI_OUTPUT_CONTROL(n)`, `TEGRA_VI_OUTPUT_FRAME_SIZE(n)`, etc. The register offset arithmetic (e.g., `0x00c4 + (n) * 44`, `0x00e0 + (n) * 24`) encodes the hardware register layout. The `output_channel` variable is introduced as `TEGRA_VI_OUT_1` everywhere for now, deferring actual dual-output usage to later patches. `vi_max_channels` is bumped from 1 to 2. **No issues.** The arithmetic offsets match the Tegra20 TRM register map. --- Generated by Claude Code Patch Reviewer