From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: arm64: dts: qcom: milos: Add display (MDSS) Date: Tue, 05 May 2026 09:35:35 +1000 Message-ID: In-Reply-To: <20260501-milos-mdss-v3-9-58bfc58c0e13@fairphone.com> References: <20260501-milos-mdss-v3-0-58bfc58c0e13@fairphone.com> <20260501-milos-mdss-v3-9-58bfc58c0e13@fairphone.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Adds the complete MDSS device tree nodes (MDSS, DPU, DSI controller, DSI PHY) to milos.dtsi, and wires up the dispcc clock controller to use the DSI PHY clocks instead of the `<0>` placeholders. The DTS matches the DT binding example from Patch 4 almost exactly (with expected differences like `#address-cells = <2>` in the actual DTS vs `<1>` in the binding example, and `status = "disabled"` in the actual nodes). ```diff - <0>, /* dsi0_phy_pll_out_byteclk */ - <0>, /* dsi0_phy_pll_out_dsiclk */ + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, ``` This correctly replaces the stub clock references in the display clock controller with the actual DSI PHY PLL outputs. The `dt-bindings/clock/qcom,dsi-phy-28nm.h` include is added for `DSI_BYTE_PLL_CLK` and `DSI_PIXEL_PLL_CLK` constants. All nodes are `status = "disabled"` by default, to be enabled by board-level DTS files. Has Reviewed-by from Konrad. No issues. --- Generated by Claude Code Patch Reviewer