From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/bridge: tc358762: Fix sync polarities Date: Sat, 16 May 2026 12:04:23 +1000 Message-ID: In-Reply-To: <20260513-tc358762-fixes-v3-9-6698b55008b9@ideasonboard.com> References: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> <20260513-tc358762-fixes-v3-9-6698b55008b9@ideasonboard.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review Fixes the polarity logic: `LCDCTRL_HSYNC_POL` makes hsync active-high, so i= t should be set for `DRM_MODE_FLAG_PHSYNC` (positive hsync), not `DRM_MODE_= FLAG_NHSYNC`. Same for vsync. The old code had this inverted. This is a real bug fix. Note that for the Raspberry Pi display which uses `= DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC`, neither flag gets set =E2=80= =94 which matches the old behavior where `NHSYNC =E2=86=92 set HSPOL` but t= he old HSPOL was actually at the wrong bit position (it was `LCDCTRL_VSDELA= Y(1)` =3D BIT(20) =3D DCLK_POL). So the old code had two bugs that partiall= y cancelled out. No issues. **Reviewed-by worthy.** --- Generated by Claude Code Patch Reviewer