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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a285192b5esm82622e87.16.2026.03.19.12.05.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Mar 2026 12:05:05 -0700 (PDT) Date: Thu, 19 Mar 2026 21:05:03 +0200 From: Dmitry Baryshkov To: Neil Armstrong Cc: Alexander Koskovich , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Jeffrey Hugo , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org Subject: Re: [PATCH v3 4/4] drm/msm/dpu: fix video mode DSC INTF timing width calculation Message-ID: References: <20260319-dsi-rgb101010-support-v3-0-85b99df2d090@pm.me> <20260319-dsi-rgb101010-support-v3-4-85b99df2d090@pm.me> <1360a31d-669e-48df-a1be-f0af4a253cd7@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1360a31d-669e-48df-a1be-f0af4a253cd7@linaro.org> X-Proofpoint-ORIG-GUID: Yr03nOrOKQz0yiwlyPHngOkoNYJ9WraF X-Authority-Analysis: v=2.4 cv=EcjFgfmC c=1 sm=1 tr=0 ts=69bc48e3 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=xqWC_Br6kY4A:10 a=kj9zAlcOel0A:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=L2_DCg_Kqtn3RnkwlLMA:9 a=CjuIK1q_8ugA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-GUID: Yr03nOrOKQz0yiwlyPHngOkoNYJ9WraF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE5MDE1MiBTYWx0ZWRfX/lh3arqqqaWV P9vrisPckVXMZuoV1eXiTOrnOW3aiI7Ncff2dcrPlIOtHx4cmn6hCuWcfwRIAffXd5SyKyuYGrX 7x3EW2qJX8XOGrgkySfTt/+zzLCJxkW5mUcUjqPDZzwAqWT86ZH3+t7bhP2bXvrBZ9sQbQe5S8p C8O1XXvdOz+9nw850KgrNdKrXxRhNKjyxCDCuL9svcGLo8LBCPoG5jIYm5OY8tKvJFQdzXr+Ffz RRkrr45ArxWEv6NDDt4AQt2/l5tRcZVa8BVpknkGjydUNqYOYAlqOs629kqial3i6nfuufgZLHA 7iE2rlHb7GXbjDNqp8uNVfgz3lwFaquV+SMq1EIZW6BbaUTAWKR5iCQ3d9b30KK4M1gUG/98fpI 5QY7ZevfdMyEp68gHTlC9iF2hImJhSvQ0Hi7jZhg3mrW0IvMMYVTKDGqbP7sqj0bleyHTbSqJbm Z2WDPvZRDG0gNJwtEgg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-19_03,2026-03-19_05,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 suspectscore=0 impostorscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603190152 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu, Mar 19, 2026 at 03:09:13PM +0100, Neil Armstrong wrote: > Hi, > > On 3/19/26 12:58, Alexander Koskovich wrote: > > Using bits_per_component * 3 as the divisor for the compressed INTF > > timing width produces constant FIFO errors for the BOE BF068MWM-TD0 > > panel due to bits_per_component being 10 which results in a divisor > > of 30 instead of 24. > > > > Regardless of the compression ratio and pixel depth, 24 bits of > > compressed data are transferred per pclk, so the divisor should > > always be 24. > > Not true with widebus, specify why 24 and because DSI widebus is not implemented yet. Support for the widebus is implemented and enable for DSI >= 2.5.0 > > > > > Signed-off-by: Alexander Koskovich > > --- > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 9 ++++----- > > 1 file changed, 4 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > > index 0ba777bda253..5419ef0be137 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > > @@ -122,19 +122,18 @@ static void drm_mode_to_intf_timing_params( > > } > > /* > > - * for DSI, if compression is enabled, then divide the horizonal active > > - * timing parameters by compression ratio. bits of 3 components(R/G/B) > > - * is compressed into bits of 1 pixel. > > + * For DSI, if DSC is enabled, 24 bits of compressed data are > > + * transferred per pclk regardless of the source pixel depth. > > */ > > if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) { > > struct drm_dsc_config *dsc = > > dpu_encoder_get_dsc_config(phys_enc->parent); > > + > Drop this change > > > /* > > * TODO: replace drm_dsc_get_bpp_int with logic to handle > > * fractional part if there is fraction > > */ > > - timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / > > - (dsc->bits_per_component * 3); > > + timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / 24; > > It would be helpful to somehow show that 24 is 8 * 3, 8 being the byte width and 3 the compression ratio. Otherwise I'd have assumed that it is bus width. > > > timing->xres = timing->width; > > } > > } > > > -- With best wishes Dmitry