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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a13d08d737sm2781938e87.88.2026.03.10.06.37.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 06:37:02 -0700 (PDT) Date: Tue, 10 Mar 2026 15:37:00 +0200 From: Dmitry Baryshkov To: Konrad Dybcio Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Konrad Dybcio Subject: Re: [PATCH] drm/msm/mdss: Add a TODO for better managing the MDSS clock power state Message-ID: References: <20260310-topic-mdss_power_todo-v1-1-59457b8b7486@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260310-topic-mdss_power_todo-v1-1-59457b8b7486@oss.qualcomm.com> X-Authority-Analysis: v=2.4 cv=H7fWAuYi c=1 sm=1 tr=0 ts=69b01e80 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=xqWC_Br6kY4A:10 a=kj9zAlcOel0A:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=fNJ4iHBr628apSTVAaYA:9 a=CjuIK1q_8ugA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-GUID: VPYL9Cbf4GHdkJOxxY4RLuEZNoNdZPK4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEwMDExOCBTYWx0ZWRfXzIircN1j94q4 YEZA5EfdP8XoRatCNwzcpqTOyWuRwzyN7PrYxSGxuUwPsGZt28WV6rWV6tNlKWG0B7jif4iVEJB lreOggIu4r+U0VijXi1Wt8DFxhhVU7qXU2yvynivLMQuWKgS1Yd0QhZMjqT/kEsDBdVB7lfhcdE UcNixX/v/r8wX0fOo+TQ4KQ1R0FKDigco0GwTFZwTp8DvZjzWaPprc/lU07hMQCqCJDpvjmu+5M yFXKrMgKC9q5i1Yv8dhhaCinQRHTspqA+G8GF0xL6nWFjzPaSrnACVBjkENwmcKb4+rGHA5ltVs fue+4FeN+zvCjauyyi9eejPDqoUeP5a2ArvOZBxNN161loPKpZMsM4+VVuppRFjCJ1k51w1jPCz Ye0VQvrG705gpPnktdltk9oZi+EKhHv9QUft74G+fXVsfWNeJWZk21UyW5Xtrm2sDkjSLGEBzxP KIOmRwPH2MG11SFE9Xw== X-Proofpoint-ORIG-GUID: VPYL9Cbf4GHdkJOxxY4RLuEZNoNdZPK4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-10_02,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 phishscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603100118 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Tue, Mar 10, 2026 at 02:20:25PM +0100, Konrad Dybcio wrote: > From: Konrad Dybcio > > There's a small window where the MDP clock could be set to a high rate > (say, from the bootloader) without a corresponding RPM(H)PD vote to > back it up. This is normally not an issue, but could be, if rmmod fails > to shut down the display driver cleanly, and the module is inserted > again, or when the providers' .sync_state has timed out. > > Mark a TODO to fix it one day. Linking the relevant discussion below. > > Link: https://lore.kernel.org/linux-arm-msm/d5c4eed5-bd87-4156-b178-2d78140ec8a9@oss.qualcomm.com/ > Signed-off-by: Konrad Dybcio > --- > drivers/gpu/drm/msm/msm_mdss.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c > index 9047e8d9ee89..b783dfec83b8 100644 > --- a/drivers/gpu/drm/msm/msm_mdss.c > +++ b/drivers/gpu/drm/msm/msm_mdss.c > @@ -262,6 +262,14 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) > icc_set_bw(msm_mdss->reg_bus_path, 0, > msm_mdss->reg_bus_bw); > > + /* > + * TODO: > + * Previous users (e.g. the bootloader) may have left this clock at a high rate, which > + * would remain set, as prepare_enable() doesn't reprogram it. This theoretically poses a > + * risk of brownout, but realistically this path is almost exclusively excercised after the > + * correct OPP has been set in one of the MDPn or DPU drivers, or during initial probe, > + * before the RPM(H)PD sync_state is done. > + */ I'd have preferred if it was not exercising 100-char limit, but there is no reason to enforce that. Reviewed-by: Dmitry Baryshkov > ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); > if (ret) { > dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret); > > --- > base-commit: fc7b1a72c6cd5cbbd989c6c32a6486e3e4e3594d > change-id: 20260310-topic-mdss_power_todo-4a19cf5f5183 > > Best regards, > -- > Konrad Dybcio > -- With best wishes Dmitry