From: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
To: Rob Clark <robin.clark@oss.qualcomm.com>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jesszhan0024@gmail.com>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Akhil P Oommen <akhilpo@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Subject: [PATCH v5 27/28] soc: qcom: ubwc: sort out the rest of the UBWC swizzle settings
Date: Wed, 20 May 2026 17:51:34 +0300 [thread overview]
Message-ID: <20260520-ubwc-rework-v5-27-72f2749bc807@oss.qualcomm.com> (raw)
In-Reply-To: <20260520-ubwc-rework-v5-0-72f2749bc807@oss.qualcomm.com>
Sort out the remaining UBWC swizzle values, using flags to control
whether level 2 and level 3 swizzling are enabled or not.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/soc/qcom/ubwc_config.c | 16 +++-------------
include/linux/soc/qcom/ubwc.h | 26 +++++++++++++-------------
2 files changed, 16 insertions(+), 26 deletions(-)
diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
index 7e321389a399..f27440d5c06f 100644
--- a/drivers/soc/qcom/ubwc_config.c
+++ b/drivers/soc/qcom/ubwc_config.c
@@ -18,16 +18,12 @@ static const struct qcom_ubwc_cfg_data no_ubwc_data = {
static const struct qcom_ubwc_cfg_data eliza_data = {
.ubwc_enc_version = UBWC_5_0,
- .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
- UBWC_SWIZZLE_ENABLE_LVL3,
/* TODO: highest_bank_bit = 14 for LP_DDR4 */
.highest_bank_bit = 15,
};
static const struct qcom_ubwc_cfg_data kaanapali_data = {
.ubwc_enc_version = UBWC_6_0,
- .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
- UBWC_SWIZZLE_ENABLE_LVL3,
.highest_bank_bit = 16,
};
@@ -48,7 +44,7 @@ static const struct qcom_ubwc_cfg_data qcm2290_data = {
static const struct qcom_ubwc_cfg_data sa8775p_data = {
.ubwc_enc_version = UBWC_4_0,
- .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL3,
+ .flags = UBWC_FLAG_DISABLE_SWIZZLE_LVL2,
.highest_bank_bit = 13,
};
@@ -119,38 +115,32 @@ static const struct qcom_ubwc_cfg_data sm8150_data = {
static const struct qcom_ubwc_cfg_data sm8250_data = {
.ubwc_enc_version = UBWC_4_0,
- .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
- UBWC_SWIZZLE_ENABLE_LVL3,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,
};
static const struct qcom_ubwc_cfg_data sm8350_data = {
.ubwc_enc_version = UBWC_4_0,
- .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
- UBWC_SWIZZLE_ENABLE_LVL3,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,
};
static const struct qcom_ubwc_cfg_data sm8550_data = {
.ubwc_enc_version = UBWC_4_0,
- .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
- UBWC_SWIZZLE_ENABLE_LVL3,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,
};
static const struct qcom_ubwc_cfg_data sm8750_data = {
.ubwc_enc_version = UBWC_5_0,
- .ubwc_swizzle = 6,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,
};
static const struct qcom_ubwc_cfg_data glymur_data = {
.ubwc_enc_version = UBWC_5_0,
- .ubwc_swizzle = 0,
+ .flags = UBWC_FLAG_DISABLE_SWIZZLE_LVL2 |
+ UBWC_FLAG_DISABLE_SWIZZLE_LVL3,
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
.highest_bank_bit = 16,
};
diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h
index 7c9506741001..a7372d9c25fb 100644
--- a/include/linux/soc/qcom/ubwc.h
+++ b/include/linux/soc/qcom/ubwc.h
@@ -14,15 +14,6 @@
struct qcom_ubwc_cfg_data {
u32 ubwc_enc_version;
- /**
- * @ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling.
- *
- * UBWC 1.0 always enables all three levels.
- * UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3.
- * UBWC 4.0 adds the optional ability to disable levels 2 & 3.
- */
- u32 ubwc_swizzle;
-
/**
* @highest_bank_bit: Highest Bank Bit
*
@@ -30,6 +21,10 @@ struct qcom_ubwc_cfg_data {
* DDR bank. This should ideally use DRAM type detection.
*/
int highest_bank_bit;
+
+ unsigned int flags;
+#define UBWC_FLAG_DISABLE_SWIZZLE_LVL2 BIT(0)
+#define UBWC_FLAG_DISABLE_SWIZZLE_LVL3 BIT(1)
};
#define UBWC_1_0 0x10000000
@@ -98,11 +93,16 @@ static inline u32 qcom_ubwc_swizzle(const struct qcom_ubwc_cfg_data *cfg)
UBWC_SWIZZLE_ENABLE_LVL2 |
UBWC_SWIZZLE_ENABLE_LVL3;
- if (cfg->ubwc_enc_version < UBWC_4_0)
- return UBWC_SWIZZLE_ENABLE_LVL2 |
- UBWC_SWIZZLE_ENABLE_LVL3;
+ u32 ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
+ UBWC_SWIZZLE_ENABLE_LVL3;
+
+ if (cfg->flags & UBWC_FLAG_DISABLE_SWIZZLE_LVL2)
+ ubwc_swizzle &= ~UBWC_SWIZZLE_ENABLE_LVL2;
+
+ if (cfg->flags & UBWC_FLAG_DISABLE_SWIZZLE_LVL3)
+ ubwc_swizzle &= ~UBWC_SWIZZLE_ENABLE_LVL3;
- return cfg->ubwc_swizzle;
+ return ubwc_swizzle;
}
static inline u32 qcom_ubwc_version_tag(const struct qcom_ubwc_cfg_data *cfg)
--
2.47.3
next prev parent reply other threads:[~2026-05-20 14:52 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-20 14:51 [PATCH v5 00/28] soc/qcom/ubwc: rework UBWC configuration database Dmitry Baryshkov
2026-05-20 14:51 ` [PATCH v5 01/28] soc: qcom: ubwc: define UBWC 3.1 Dmitry Baryshkov
2026-05-25 11:41 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 02/28] soc: qcom: ubwc: define helper for MDSS and Adreno drivers Dmitry Baryshkov
2026-05-25 11:41 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 03/28] soc: qcom: ubwc: add helper controlling AMSBC enablement Dmitry Baryshkov
2026-05-25 11:41 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 04/28] drm/msm/adreno: Trust the SSoT UBWC config Dmitry Baryshkov
2026-05-25 11:41 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 05/28] drm/msm/adreno: use qcom_ubwc_version_tag() helper Dmitry Baryshkov
2026-05-25 11:41 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 06/28] drm/msm/mdss: " Dmitry Baryshkov
2026-05-25 11:41 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 07/28] drm/msm/adreno: use new helper to set min_acc length Dmitry Baryshkov
2026-05-25 11:41 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 08/28] drm/msm/mdss: " Dmitry Baryshkov
2026-05-25 11:41 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 09/28] drm/msm/adreno: use new helper to set macrotile_mode Dmitry Baryshkov
2026-05-25 11:41 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 10/28] drm/msm/mdss: " Dmitry Baryshkov
2026-05-25 11:41 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 11/28] drm/msm/mdss: use new helper to set UBWC bank spreading Dmitry Baryshkov
2026-05-25 11:41 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 12/28] drm/msm/adreno: use new helper to set ubwc_swizzle Dmitry Baryshkov
2026-05-25 11:41 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 13/28] drm/msm/dpu: " Dmitry Baryshkov
2026-05-25 11:41 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 14/28] drm/msm/mdss: " Dmitry Baryshkov
2026-05-25 11:41 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 15/28] drm/msm/adreno: write reserved UBWC-related bits Dmitry Baryshkov
2026-05-25 11:41 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 16/28] drm/msm/adreno: set fp16compoptdis for UBWC 3.0 formats Dmitry Baryshkov
2026-05-25 11:41 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 17/28] drm/msm/adreno: use new helper to set amsbc Dmitry Baryshkov
2026-05-25 11:42 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 18/28] drm/msm/adreno: use version ranges in A8xx UBWC code Dmitry Baryshkov
2026-05-25 11:42 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 19/28] drm/msm/mdss: use new helper to set amsbc Dmitry Baryshkov
2026-05-25 11:42 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 20/28] drm/msm/dpu: drop ubwc_dec_version Dmitry Baryshkov
2026-05-25 11:42 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 21/28] drm/msm/dpu: invert the order of UBWC checks Dmitry Baryshkov
2026-05-25 11:42 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 22/28] soc: qcom: ubwc: set min_acc length to 64 for all UBWC 1.0 targets Dmitry Baryshkov
2026-05-25 11:42 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 23/28] soc: qcom: ubwc: drop ubwc_dec_version Dmitry Baryshkov
2026-05-25 11:42 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 24/28] soc: qcom: ubwc: drop ubwc_bank_spread Dmitry Baryshkov
2026-05-25 11:42 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 25/28] soc: qcom: ubwc: drop macrotile_mode from the database Dmitry Baryshkov
2026-05-25 11:42 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 26/28] soc: qcom: ubwc: use fixed values for UBWC swizzle for UBWC < 4.0 Dmitry Baryshkov
2026-05-25 11:42 ` Claude review: " Claude Code Review Bot
2026-05-20 14:51 ` Dmitry Baryshkov [this message]
2026-05-25 11:42 ` Claude review: soc: qcom: ubwc: sort out the rest of the UBWC swizzle settings Claude Code Review Bot
2026-05-20 14:51 ` [PATCH v5 28/28] soc: qcom: ubwc: deduplicate UBWC configuration data Dmitry Baryshkov
2026-05-25 11:42 ` Claude review: " Claude Code Review Bot
2026-05-25 11:41 ` Claude review: soc/qcom/ubwc: rework UBWC configuration database Claude Code Review Bot
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