Claude review: drm/rockchip: vop2: Add clock rate mode check

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Overall Series Review

Subject: drm/rockchip: vop2: Add clock rate mode check
Author: Sebastian Reichel <sebastian.reichel@collabora.com>
Patches: 1
Reviewed: 2026-04-12T10:38:57.670124

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This is a single RFC patch that adds pixel clock rate validation to the Rockchip VOP2 display driver's `mode_valid` callback. The approach is straightforward and correct in principle: store a per-video-port maximum pixel clock rate and reject modes that exceed it. The implementation is clean and minimal.

The main area of concern — which the author explicitly flags via the RFC tag — is the correctness of the `* 4` multiplier applied to the 600 MHz base clock for certain video ports. The rk3588 `* 4` multiplier is well-supported by the existing code comment at `rockchip_vop2_reg.c:1572` ("4 pixclk/cycle on rk3588") and the `dclk_core_rate = v_pixclk >> 2` logic. The rk3576 case is less clear.

**Verdict**: The code change itself is correct and well-structured. The numerical values need confirmation from the hardware vendor (Andy Yan), particularly for rk3576. A couple of minor issues noted below.

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