Claude review: Initial support Cadence MHDP8501(HDMI/DP) for i.MX8MQ

[Claude Code Review Bot <claude-review@example.com>]

Overall Series Review

Subject: Initial support Cadence MHDP8501(HDMI/DP) for i.MX8MQ
Author: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Patches: 9
Reviewed: 2026-05-25T22:48:47.938216

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This is v23 of a patch series adding initial Cadence MHDP8501 HDMI/DP bridge and HDP-TX PHY support for the i.MX8MQ SoC. The series has been through extensive review over 23 revisions and is well-structured:

1. Extract shared mailbox helpers into `drivers/soc/cadence/`
2. Refactor existing mhdp8546 to use the new helpers
3-4. PHY DT binding + driver
5-6. Bridge DT binding + driver
7-8. DTS enablement

The overall architecture is sound: the mailbox layer is properly shared, the PHY child-node approach avoids duplicating MMIO mappings, and the bridge driver uses modern DRM atomic APIs. The series clearly benefited from extensive review — most common pitfalls have been addressed. However, several issues remain across the patches.

**Key concerns:**
- Potential race between IRQ handling and device removal in the mhdp8501 bridge driver
- The `phy_powered` flag lacks sufficient synchronization in certain paths
- The HDMI I2C adapter is extremely limited (only SCDC slave) — this should be clearly documented in the code
- Copyright dates still say 2023-2024 despite being submitted in 2026
- The mhdp8546 patch adds `struct cdns_mhdp_base base` to `cdns_mhdp_device` while keeping the existing `regs`/`sapb_regs` fields, creating data duplication

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